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Angel Pons6e5aabd2020-03-23 23:44:42 +01001## SPDX-License-Identifier: GPL-2.0-only
Stefan Reinauer00636b02012-04-04 00:08:51 +02002
Alexandru Gagniucecf2eb42015-09-28 21:39:12 -07003config NORTHBRIDGE_INTEL_SANDYBRIDGE
Vladimir Serbinenko309fc4c2014-08-24 22:35:29 +02004 bool
Arthur Heymans7539b8c2017-12-24 10:42:57 +01005 select CACHE_MRC_SETTINGS
Vladimir Serbinenko309fc4c2014-08-24 22:35:29 +02006 select CPU_INTEL_MODEL_206AX
7 select HAVE_DEBUG_RAM_SETUP
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +01008 select INTEL_GMA_ACPI
Vladimir Serbinenko309fc4c2014-08-24 22:35:29 +02009
Nico Huber772a1542019-05-10 16:48:14 +020010if NORTHBRIDGE_INTEL_SANDYBRIDGE
Vladimir Serbinenko144eea02016-02-10 02:36:04 +010011
Elyes Haouas9ee9cd32022-10-30 10:20:33 +010012config NORTHBRIDGE_SPECIFIC_OPTIONS
13 def_bool y
14 select NO_DDR5
15 select NO_LPDDR4
16 select NO_DDR4
17 select NO_DDR2
18 select USE_DDR3
19
Arthur Heymans691d58f2021-08-11 13:42:40 +020020config CHIPSET_DEVICETREE
21 default "northbridge/intel/sandybridge/chipset.cb"
22
Patrick Rudolph1ee3dbc2020-02-28 13:11:13 +010023config SANDYBRIDGE_VBOOT_IN_ROMSTAGE
24 bool
25 default n
26 help
27 Selected by boards to force VBOOT_STARTS_IN_ROMSTAGE.
28
29config SANDYBRIDGE_VBOOT_IN_BOOTBLOCK
30 depends on VBOOT
31 depends on !SANDYBRIDGE_VBOOT_IN_ROMSTAGE
32 bool "Start verstage in bootblock"
33 default y
34 select VBOOT_STARTS_IN_BOOTBLOCK
Patrick Rudolph1ee3dbc2020-02-28 13:11:13 +010035 help
36 Sandy Bridge can either start verstage in a separate stage
37 right after the bootblock has run or it can start it
38 after romstage for compatibility reasons.
39 Sandy Bridge however uses a mrc.bin to initialize memory which
40 needs to be located at a fixed offset. Therefore even with
41 a separate verstage starting after the bootblock that same
42 binary is used meaning a jump is made from RW to the RO region
43 and back to the RW region after the binary is done.
44
Julius Werner1210b412017-03-27 19:26:32 -070045config VBOOT
Patrick Rudolph1ee3dbc2020-02-28 13:11:13 +010046 select VBOOT_MUST_REQUEST_DISPLAY
47 select VBOOT_STARTS_IN_ROMSTAGE if !SANDYBRIDGE_VBOOT_IN_BOOTBLOCK
Julius Werner1210b412017-03-27 19:26:32 -070048
Vladimir Serbinenko144eea02016-02-10 02:36:04 +010049config USE_NATIVE_RAMINIT
50 bool "Use native raminit"
51 default y
52 help
53 Select if you want to use coreboot implementation of raminit rather than
54 System Agent/MRC.bin. You should answer Y.
Stefan Reinauer00636b02012-04-04 00:08:51 +020055
Patrick Rudolphb794a692017-08-08 13:13:51 +020056config NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES
57 bool "Ignore vendor programmed fuses that limit max. DRAM frequency"
58 default n
59 depends on USE_NATIVE_RAMINIT
60 help
61 Ignore the mainboard's vendor programmed fuses that might limit the
62 maximum DRAM frequency. By selecting this option the fuses will be
63 ignored and the only limits on DRAM frequency are set by RAM's SPD and
64 hard fuses in southbridge's clockgen.
65 Disabled by default as it might causes system instability.
66 Handle with care!
67
Vagiz Trakhanov771be482017-10-02 10:02:35 +000068config NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS
69 bool "Ignore XMP profile max DIMMs per channel"
70 default n
71 depends on USE_NATIVE_RAMINIT
72 help
73 Ignore the max DIMMs per channel restriciton defined in XMP profiles.
74 Disabled by default as it might cause system instability.
75 Handle with care!
76
Angel Pons3170e9c2020-12-12 16:22:18 +010077config NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE
78 bool "Ignore XMP profile requested voltage"
79 default n
80 depends on USE_NATIVE_RAMINIT
81 help
82 Native raminit only supports 1.5V operation, but there are DIMMs
83 which request 1.65V operation in XMP profiles. This option allows
84 raminit to use these XMP profiles anyway, instead of falling back
85 to non-XMP settings.
86 Disabled by default because it allows forcing memory to run out of
87 specification. Consider this to be an overclocking option.
88 Handle with care!
89
Martin Roth59ff3402016-02-09 09:06:46 -070090config CBFS_SIZE
Martin Roth59ff3402016-02-09 09:06:46 -070091 default 0x100000
92
Stefan Reinauer00636b02012-04-04 00:08:51 +020093config VGA_BIOS_ID
94 string
95 default "8086,0106"
96
Shelley Chen4e9bb332021-10-20 15:43:45 -070097config ECAM_MMCONF_BASE_ADDRESS
Nico Huber2b5c0212017-07-29 01:10:49 +020098 default 0xf0000000
99 help
Arthur Heymans742a0e92018-01-29 16:34:46 +0100100 The MRC blob requires it to be at 0xf0000000.
Nico Huber2b5c0212017-07-29 01:10:49 +0200101
Shelley Chen4e9bb332021-10-20 15:43:45 -0700102config ECAM_MMCONF_BUS_NUMBER
Angel Pons10f9b832021-01-20 14:58:32 +0100103 int
104 default 64
105
Stefan Reinauer00636b02012-04-04 00:08:51 +0200106config DCACHE_RAM_BASE
107 hex
Kyösti Mälkki9551bed2016-07-20 10:49:38 +0300108 default 0xfefe0000
Stefan Reinauer00636b02012-04-04 00:08:51 +0200109
Arthur Heymans67d59d12019-11-16 20:06:20 +0100110config DCACHE_BSP_STACK_SIZE
111 hex
Arthur Heymans8d821092019-11-25 06:56:04 +0100112 default 0x10000
113 help
114 The amount of BSP stack anticipated in bootblock and
115 other stages.
Arthur Heymans01c83a22019-06-05 13:36:55 +0200116
117if USE_NATIVE_RAMINIT
118
Stefan Reinauer00636b02012-04-04 00:08:51 +0200119config DCACHE_RAM_SIZE
120 hex
121 default 0x20000
122
Kyösti Mälkki9551bed2016-07-20 10:49:38 +0300123config DCACHE_RAM_MRC_VAR_SIZE
124 hex
125 default 0x0
126
Angel Pons09fc4b92020-11-19 12:02:07 +0100127config RAMINIT_ALWAYS_ALLOW_DLL_OFF
128 bool "Also enable memory DLL-off mode on desktops and servers"
129 default n
130 help
131 If enabled, allow enabling DLL-off mode for platforms other than
132 mobile. Saves power at the expense of higher exit latencies. Has
133 no effect on mobile platforms, where DLL-off is always allowed.
134 Power down is disabled for stability when running at high clocks.
135
Patrick Rudolphdd662872017-10-28 18:20:11 +0200136config RAMINIT_ENABLE_ECC
137 bool "Enable ECC if supported"
138 default y
139 help
140 Enable ECC if supported by both, host and RAM.
141
Kyösti Mälkki9551bed2016-07-20 10:49:38 +0300142endif # USE_NATIVE_RAMINIT
143
144if !USE_NATIVE_RAMINIT
145
Kyösti Mälkki9551bed2016-07-20 10:49:38 +0300146config DCACHE_RAM_SIZE
147 hex
Arthur Heymans01c83a22019-06-05 13:36:55 +0200148 default 0x17000
Kyösti Mälkkifbdb0852013-07-01 11:21:53 +0300149
Stefan Reinauer00636b02012-04-04 00:08:51 +0200150config DCACHE_RAM_MRC_VAR_SIZE
151 hex
Arthur Heymans01c83a22019-06-05 13:36:55 +0200152 default 0x9000
Stefan Reinauer00636b02012-04-04 00:08:51 +0200153
Stefan Reinauer00636b02012-04-04 00:08:51 +0200154config MRC_FILE
155 string "Intel System Agent path and filename"
Patrick Georgi26e24cc2015-05-05 22:27:25 +0200156 default "3rdparty/blobs/northbridge/intel/sandybridge/systemagent-r6.bin"
Stefan Reinauer00636b02012-04-04 00:08:51 +0200157 help
158 The path and filename of the file to use as System Agent
159 binary.
160
Kyösti Mälkki9551bed2016-07-20 10:49:38 +0300161endif # !USE_NATIVE_RAMINIT
Kyösti Mälkki0306e6a2016-06-23 12:41:40 +0300162
Nico Huber612a8672019-02-19 19:11:29 +0100163config INTEL_GMA_BCLV_OFFSET
164 default 0x48254
165
Angel Ponsd9e58dc2021-01-20 01:22:20 +0100166config FIXED_MCHBAR_MMIO_BASE
167 default 0xfed10000
168
169config FIXED_DMIBAR_MMIO_BASE
170 default 0xfed18000
171
172config FIXED_EPBAR_MMIO_BASE
173 default 0xfed19000
174
Stefan Reinauer00636b02012-04-04 00:08:51 +0200175endif