Blame - src/northbridge/intel/sandybridge/Kconfig - coreboot

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Stefan Reinauer	00636b0	2012-04-04 00:08:51 +0200	[diff] [blame]	1	##
				2	## This file is part of the coreboot project.
				3	##
				4	## Copyright (C) 2010 Google Inc.
				5	##
				6	## This program is free software; you can redistribute it and/or modify
				7	## it under the terms of the GNU General Public License as published by
				8	## the Free Software Foundation; version 2 of the License.
				9	##
				10	## This program is distributed in the hope that it will be useful,
				11	## but WITHOUT ANY WARRANTY; without even the implied warranty of
				12	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
				13	## GNU General Public License for more details.
				14	##
				15	## You should have received a copy of the GNU General Public License
				16	## along with this program; if not, write to the Free Software
Paul Menzel	a46a712	2013-02-23 18:37:27 +0100	[diff] [blame]	17	## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Stefan Reinauer	00636b0	2012-04-04 00:08:51 +0200	[diff] [blame]	18	##
				19
				20	config NORTHBRIDGE_INTEL_SANDYBRIDGE
				21	bool
				22	select CACHE_MRC_BIN
Kyösti Mälkki	fbdb085	2013-07-01 11:21:53 +0300	[diff] [blame^]	23	select MMCONF_SUPPORT
				24	select MMCONF_SUPPORT_DEFAULT
Stefan Reinauer	00636b0	2012-04-04 00:08:51 +0200	[diff] [blame]	25	select CPU_INTEL_MODEL_206AX
				26
				27	config NORTHBRIDGE_INTEL_IVYBRIDGE
				28	bool
				29	select CACHE_MRC_BIN
Kyösti Mälkki	fbdb085	2013-07-01 11:21:53 +0300	[diff] [blame^]	30	select MMCONF_SUPPORT
				31	select MMCONF_SUPPORT_DEFAULT
Stefan Reinauer	00636b0	2012-04-04 00:08:51 +0200	[diff] [blame]	32	select CPU_INTEL_MODEL_306AX
				33
				34	if NORTHBRIDGE_INTEL_SANDYBRIDGE
				35
				36	config VGA_BIOS_ID
				37	string
				38	default "8086,0106"
				39
				40	config CACHE_MRC_SIZE_KB
				41	int
				42	default 256
				43
Stefan Reinauer	1244f4b	2012-05-10 11:31:40 -0700	[diff] [blame]	44	# FIXME: build from rom size
				45	config MRC_CACHE_BASE
				46	hex
				47	default 0xff800000
				48
				49	config MRC_CACHE_LOCATION
				50	hex
Stefan Reinauer	357bb2d	2012-08-09 13:44:38 -0700	[diff] [blame]	51	depends on !CHROMEOS
Stefan Reinauer	1244f4b	2012-05-10 11:31:40 -0700	[diff] [blame]	52	default 0x1ec000
				53
				54	config MRC_CACHE_SIZE
				55	hex
Stefan Reinauer	357bb2d	2012-08-09 13:44:38 -0700	[diff] [blame]	56	depends on !CHROMEOS
Stefan Reinauer	1244f4b	2012-05-10 11:31:40 -0700	[diff] [blame]	57	default 0x10000
				58
Stefan Reinauer	00636b0	2012-04-04 00:08:51 +0200	[diff] [blame]	59	config DCACHE_RAM_BASE
				60	hex
				61	default 0xff7f0000
				62
				63	config DCACHE_RAM_SIZE
				64	hex
				65	default 0x10000
				66
				67	endif
				68
				69	if NORTHBRIDGE_INTEL_IVYBRIDGE
				70
				71	config VGA_BIOS_ID
				72	string
				73	default "8086,0166"
				74
				75	config EXTERNAL_MRC_BLOB
				76	bool
				77	default n
				78
				79	config CACHE_MRC_SIZE_KB
				80	int
				81	default 512
				82
Stefan Reinauer	4821489	2012-06-06 13:24:32 -0700	[diff] [blame]	83	# FIXME: build from rom size
				84	config MRC_CACHE_BASE
				85	hex
				86	default 0xff800000
				87
				88	config MRC_CACHE_LOCATION
				89	hex
Stefan Reinauer	357bb2d	2012-08-09 13:44:38 -0700	[diff] [blame]	90	depends on !CHROMEOS
Stefan Reinauer	4821489	2012-06-06 13:24:32 -0700	[diff] [blame]	91	default 0x370000
				92
				93	config MRC_CACHE_SIZE
				94	hex
Stefan Reinauer	357bb2d	2012-08-09 13:44:38 -0700	[diff] [blame]	95	depends on !CHROMEOS
Stefan Reinauer	4821489	2012-06-06 13:24:32 -0700	[diff] [blame]	96	default 0x10000
				97
Stefan Reinauer	00636b0	2012-04-04 00:08:51 +0200	[diff] [blame]	98	config DCACHE_RAM_BASE
				99	hex
				100	default 0xff7e0000
				101
				102	config DCACHE_RAM_SIZE
				103	hex
				104	default 0x20000
				105
				106	endif
				107
				108	if NORTHBRIDGE_INTEL_SANDYBRIDGE \|\| NORTHBRIDGE_INTEL_IVYBRIDGE
				109
Kyösti Mälkki	fbdb085	2013-07-01 11:21:53 +0300	[diff] [blame^]	110	config BOOTBLOCK_NORTHBRIDGE_INIT
				111	string
				112	default "northbridge/intel/sandybridge/bootblock.c"
				113
Stefan Reinauer	00636b0	2012-04-04 00:08:51 +0200	[diff] [blame]	114	config DCACHE_RAM_MRC_VAR_SIZE
				115	hex
				116	default 0x4000
				117
				118	config HAVE_MRC
				119	bool "Add a System Agent binary"
				120	help
				121	Select this option to add a System Agent binary to
				122	the resulting coreboot image.
				123
				124	Note: Without this binary coreboot will not work
				125
				126	config MRC_FILE
				127	string "Intel System Agent path and filename"
				128	depends on HAVE_MRC
Stefan Reinauer	1cc3416	2013-06-27 15:59:18 -0700	[diff] [blame]	129	default "systemagent-r6.bin"
Stefan Reinauer	00636b0	2012-04-04 00:08:51 +0200	[diff] [blame]	130	help
				131	The path and filename of the file to use as System Agent
				132	binary.
				133
Stefan Reinauer	a1ea822	2012-08-15 16:28:48 -0700	[diff] [blame]	134	config CBFS_SIZE
				135	hex "Size of CBFS filesystem in ROM"
				136	default 0x100000
				137	help
				138	On Sandybridge and Ivybridge systems the firmware image has to
				139	store a lot more than just coreboot, including:
				140	- a firmware descriptor
				141	- Intel Management Engine firmware
				142	- MRC cache information
				143	This option allows to limit the size of the CBFS portion in the
				144	firmware image.
				145
Stefan Reinauer	00636b0	2012-04-04 00:08:51 +0200	[diff] [blame]	146	endif