| commit | 691d58f9996d2ff3820b2c08646e98f16bbde2ee | [log] [tgz] |
|---|---|---|
| author | Arthur Heymans <arthur@aheymans.xyz> | Wed Aug 11 13:42:40 2021 +0200 |
| committer | Martin L Roth <gaumless@gmail.com> | Wed Nov 30 15:19:06 2022 +0000 |
| tree | 043767ab2d786e0736961513a2b7d3012a5ef8ca | |
| parent | 6cecb0d963dd8df9440487690c11a6da75d8b70f [diff] [blame] |
nb/intel/sandybridge: Add a chipset devicetree This only moves CPU configuration to a common place. Other PCI devices can be done in follow-ups. Change-Id: I9c5b6f25b779e28b6719cf70455ff0f1a916ad87 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56912 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 551714a..bbe8ac4 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -17,6 +17,9 @@ select NO_DDR2 select USE_DDR3 +config CHIPSET_DEVICETREE + default "northbridge/intel/sandybridge/chipset.cb" + config SANDYBRIDGE_VBOOT_IN_ROMSTAGE bool default n