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Angel Pons6e5aabd2020-03-23 23:44:42 +01001## SPDX-License-Identifier: GPL-2.0-only
Stefan Reinauer00636b02012-04-04 00:08:51 +02002
Alexandru Gagniucecf2eb42015-09-28 21:39:12 -07003config NORTHBRIDGE_INTEL_SANDYBRIDGE
Vladimir Serbinenko309fc4c2014-08-24 22:35:29 +02004 bool
Arthur Heymans7539b8c2017-12-24 10:42:57 +01005 select CACHE_MRC_SETTINGS
Vladimir Serbinenko309fc4c2014-08-24 22:35:29 +02006 select CPU_INTEL_MODEL_206AX
7 select HAVE_DEBUG_RAM_SETUP
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +01008 select INTEL_GMA_ACPI
Elyes Haouas9ee9cd32022-10-30 10:20:33 +01009 select NO_DDR5
10 select NO_LPDDR4
11 select NO_DDR4
12 select NO_DDR2
13 select USE_DDR3
14
Elyes Haouasd2ebc4d2023-01-02 15:28:41 +010015if NORTHBRIDGE_INTEL_SANDYBRIDGE
16
Arthur Heymans691d58f2021-08-11 13:42:40 +020017config CHIPSET_DEVICETREE
18 default "northbridge/intel/sandybridge/chipset.cb"
19
Patrick Rudolph1ee3dbc2020-02-28 13:11:13 +010020config SANDYBRIDGE_VBOOT_IN_ROMSTAGE
21 bool
22 default n
23 help
24 Selected by boards to force VBOOT_STARTS_IN_ROMSTAGE.
25
26config SANDYBRIDGE_VBOOT_IN_BOOTBLOCK
27 depends on VBOOT
28 depends on !SANDYBRIDGE_VBOOT_IN_ROMSTAGE
29 bool "Start verstage in bootblock"
30 default y
31 select VBOOT_STARTS_IN_BOOTBLOCK
Patrick Rudolph1ee3dbc2020-02-28 13:11:13 +010032 help
33 Sandy Bridge can either start verstage in a separate stage
34 right after the bootblock has run or it can start it
35 after romstage for compatibility reasons.
36 Sandy Bridge however uses a mrc.bin to initialize memory which
37 needs to be located at a fixed offset. Therefore even with
38 a separate verstage starting after the bootblock that same
39 binary is used meaning a jump is made from RW to the RO region
40 and back to the RW region after the binary is done.
41
Julius Werner1210b412017-03-27 19:26:32 -070042config VBOOT
Patrick Rudolph1ee3dbc2020-02-28 13:11:13 +010043 select VBOOT_MUST_REQUEST_DISPLAY
44 select VBOOT_STARTS_IN_ROMSTAGE if !SANDYBRIDGE_VBOOT_IN_BOOTBLOCK
Julius Werner1210b412017-03-27 19:26:32 -070045
Vladimir Serbinenko144eea02016-02-10 02:36:04 +010046config USE_NATIVE_RAMINIT
47 bool "Use native raminit"
48 default y
49 help
50 Select if you want to use coreboot implementation of raminit rather than
51 System Agent/MRC.bin. You should answer Y.
Stefan Reinauer00636b02012-04-04 00:08:51 +020052
Patrick Rudolphb794a692017-08-08 13:13:51 +020053config NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES
54 bool "Ignore vendor programmed fuses that limit max. DRAM frequency"
55 default n
56 depends on USE_NATIVE_RAMINIT
57 help
58 Ignore the mainboard's vendor programmed fuses that might limit the
59 maximum DRAM frequency. By selecting this option the fuses will be
60 ignored and the only limits on DRAM frequency are set by RAM's SPD and
61 hard fuses in southbridge's clockgen.
62 Disabled by default as it might causes system instability.
63 Handle with care!
64
Vagiz Trakhanov771be482017-10-02 10:02:35 +000065config NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS
66 bool "Ignore XMP profile max DIMMs per channel"
67 default n
68 depends on USE_NATIVE_RAMINIT
69 help
70 Ignore the max DIMMs per channel restriciton defined in XMP profiles.
71 Disabled by default as it might cause system instability.
72 Handle with care!
73
Angel Pons3170e9c2020-12-12 16:22:18 +010074config NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE
75 bool "Ignore XMP profile requested voltage"
76 default n
77 depends on USE_NATIVE_RAMINIT
78 help
79 Native raminit only supports 1.5V operation, but there are DIMMs
80 which request 1.65V operation in XMP profiles. This option allows
81 raminit to use these XMP profiles anyway, instead of falling back
82 to non-XMP settings.
83 Disabled by default because it allows forcing memory to run out of
84 specification. Consider this to be an overclocking option.
85 Handle with care!
86
Martin Roth59ff3402016-02-09 09:06:46 -070087config CBFS_SIZE
Martin Roth59ff3402016-02-09 09:06:46 -070088 default 0x100000
89
Stefan Reinauer00636b02012-04-04 00:08:51 +020090config VGA_BIOS_ID
91 string
92 default "8086,0106"
93
Shelley Chen4e9bb332021-10-20 15:43:45 -070094config ECAM_MMCONF_BASE_ADDRESS
Nico Huber2b5c0212017-07-29 01:10:49 +020095 default 0xf0000000
96 help
Arthur Heymans742a0e92018-01-29 16:34:46 +010097 The MRC blob requires it to be at 0xf0000000.
Nico Huber2b5c0212017-07-29 01:10:49 +020098
Shelley Chen4e9bb332021-10-20 15:43:45 -070099config ECAM_MMCONF_BUS_NUMBER
Angel Pons10f9b832021-01-20 14:58:32 +0100100 int
101 default 64
102
Stefan Reinauer00636b02012-04-04 00:08:51 +0200103config DCACHE_RAM_BASE
104 hex
Kyösti Mälkki9551bed2016-07-20 10:49:38 +0300105 default 0xfefe0000
Stefan Reinauer00636b02012-04-04 00:08:51 +0200106
Arthur Heymans67d59d12019-11-16 20:06:20 +0100107config DCACHE_BSP_STACK_SIZE
108 hex
Arthur Heymans8d821092019-11-25 06:56:04 +0100109 default 0x10000
110 help
111 The amount of BSP stack anticipated in bootblock and
112 other stages.
Arthur Heymans01c83a22019-06-05 13:36:55 +0200113
114if USE_NATIVE_RAMINIT
115
Stefan Reinauer00636b02012-04-04 00:08:51 +0200116config DCACHE_RAM_SIZE
117 hex
118 default 0x20000
119
Kyösti Mälkki9551bed2016-07-20 10:49:38 +0300120config DCACHE_RAM_MRC_VAR_SIZE
121 hex
122 default 0x0
123
Angel Pons09fc4b92020-11-19 12:02:07 +0100124config RAMINIT_ALWAYS_ALLOW_DLL_OFF
125 bool "Also enable memory DLL-off mode on desktops and servers"
126 default n
127 help
128 If enabled, allow enabling DLL-off mode for platforms other than
129 mobile. Saves power at the expense of higher exit latencies. Has
130 no effect on mobile platforms, where DLL-off is always allowed.
131 Power down is disabled for stability when running at high clocks.
132
Patrick Rudolphdd662872017-10-28 18:20:11 +0200133config RAMINIT_ENABLE_ECC
134 bool "Enable ECC if supported"
135 default y
136 help
137 Enable ECC if supported by both, host and RAM.
138
Kyösti Mälkki9551bed2016-07-20 10:49:38 +0300139endif # USE_NATIVE_RAMINIT
140
141if !USE_NATIVE_RAMINIT
142
Kyösti Mälkki9551bed2016-07-20 10:49:38 +0300143config DCACHE_RAM_SIZE
144 hex
Arthur Heymans01c83a22019-06-05 13:36:55 +0200145 default 0x17000
Kyösti Mälkkifbdb0852013-07-01 11:21:53 +0300146
Stefan Reinauer00636b02012-04-04 00:08:51 +0200147config DCACHE_RAM_MRC_VAR_SIZE
148 hex
Arthur Heymans01c83a22019-06-05 13:36:55 +0200149 default 0x9000
Stefan Reinauer00636b02012-04-04 00:08:51 +0200150
Stefan Reinauer00636b02012-04-04 00:08:51 +0200151config MRC_FILE
152 string "Intel System Agent path and filename"
Patrick Georgi26e24cc2015-05-05 22:27:25 +0200153 default "3rdparty/blobs/northbridge/intel/sandybridge/systemagent-r6.bin"
Stefan Reinauer00636b02012-04-04 00:08:51 +0200154 help
155 The path and filename of the file to use as System Agent
156 binary.
157
Kyösti Mälkki9551bed2016-07-20 10:49:38 +0300158endif # !USE_NATIVE_RAMINIT
Kyösti Mälkki0306e6a2016-06-23 12:41:40 +0300159
Nico Huber612a8672019-02-19 19:11:29 +0100160config INTEL_GMA_BCLV_OFFSET
161 default 0x48254
162
Angel Ponsd9e58dc2021-01-20 01:22:20 +0100163config FIXED_MCHBAR_MMIO_BASE
164 default 0xfed10000
165
166config FIXED_DMIBAR_MMIO_BASE
167 default 0xfed18000
168
169config FIXED_EPBAR_MMIO_BASE
170 default 0xfed19000
171
Stefan Reinauer00636b02012-04-04 00:08:51 +0200172endif