Angel Pons | f23ae0b | 2020-04-02 23:48:12 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 2 | |
Angel Pons | 45f448f | 2020-07-03 14:46:47 +0200 | [diff] [blame] | 3 | #include <arch/romstage.h> |
Angel Pons | 90ae089 | 2021-03-12 17:00:52 +0100 | [diff] [blame] | 4 | #include <cbfs.h> |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 5 | #include <console/console.h> |
Patrick Rudolph | 45022ae | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 6 | #include <cf9_reset.h> |
Angel Pons | 39a6093 | 2020-07-04 01:07:24 +0200 | [diff] [blame] | 7 | #include <device/device.h> |
Angel Pons | 6c49f40 | 2020-08-28 02:02:00 +0200 | [diff] [blame] | 8 | #include <device/mmio.h> |
Angel Pons | 30931f5 | 2021-03-12 13:06:45 +0100 | [diff] [blame] | 9 | #include <elog.h> |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 10 | #include <timestamp.h> |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 11 | #include <cpu/x86/lapic.h> |
Kyösti Mälkki | 465eff6 | 2016-06-15 06:07:55 +0300 | [diff] [blame] | 12 | #include <cbmem.h> |
Elyes HAOUAS | d26844c | 2019-06-21 07:31:40 +0200 | [diff] [blame] | 13 | #include <commonlib/helpers.h> |
Aaron Durbin | bf396ff | 2013-02-11 21:50:35 -0600 | [diff] [blame] | 14 | #include <romstage_handoff.h> |
Angel Pons | 6c49f40 | 2020-08-28 02:02:00 +0200 | [diff] [blame] | 15 | #include <security/intel/txt/txt.h> |
| 16 | #include <security/intel/txt/txt_register.h> |
Angel Pons | 2e25ac6 | 2020-07-03 12:06:04 +0200 | [diff] [blame] | 17 | #include <cpu/intel/haswell/haswell.h> |
Angel Pons | 8aab787 | 2020-07-04 01:24:59 +0200 | [diff] [blame] | 18 | #include <northbridge/intel/haswell/chip.h> |
Elyes HAOUAS | 65bb543 | 2018-07-03 14:59:50 +0200 | [diff] [blame] | 19 | #include <northbridge/intel/haswell/haswell.h> |
| 20 | #include <northbridge/intel/haswell/raminit.h> |
Angel Pons | 30931f5 | 2021-03-12 13:06:45 +0100 | [diff] [blame] | 21 | #include <southbridge/intel/common/pmclib.h> |
Elyes HAOUAS | 65bb543 | 2018-07-03 14:59:50 +0200 | [diff] [blame] | 22 | #include <southbridge/intel/lynxpoint/pch.h> |
| 23 | #include <southbridge/intel/lynxpoint/me.h> |
Angel Pons | 33b59c9 | 2021-02-11 13:42:20 +0100 | [diff] [blame] | 24 | #include <string.h> |
Angel Pons | 90ae089 | 2021-03-12 17:00:52 +0100 | [diff] [blame] | 25 | #include <types.h> |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 26 | |
Angel Pons | 6eea191 | 2020-07-03 14:14:30 +0200 | [diff] [blame] | 27 | /* Copy SPD data for on-board memory */ |
Angel Pons | 90ae089 | 2021-03-12 17:00:52 +0100 | [diff] [blame] | 28 | static void copy_spd(struct pei_data *pei_data, struct spd_info *spdi) |
Angel Pons | 6eea191 | 2020-07-03 14:14:30 +0200 | [diff] [blame] | 29 | { |
Angel Pons | 90ae089 | 2021-03-12 17:00:52 +0100 | [diff] [blame] | 30 | if (!CONFIG(HAVE_SPD_IN_CBFS)) |
| 31 | return; |
| 32 | |
| 33 | printk(BIOS_DEBUG, "SPD index %d\n", spdi->spd_index); |
| 34 | |
| 35 | size_t spd_file_len; |
| 36 | uint8_t *spd_file = cbfs_map("spd.bin", &spd_file_len); |
| 37 | |
| 38 | if (!spd_file) |
| 39 | die("SPD data not found."); |
| 40 | |
| 41 | if (spd_file_len < ((spdi->spd_index + 1) * SPD_LEN)) { |
| 42 | printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); |
| 43 | spdi->spd_index = 0; |
| 44 | } |
| 45 | |
| 46 | if (spd_file_len < SPD_LEN) |
| 47 | die("Missing SPD data."); |
| 48 | |
| 49 | /* MRC only uses index 0, but coreboot uses the other indices */ |
| 50 | memcpy(pei_data->spd_data[0], spd_file + (spdi->spd_index * SPD_LEN), SPD_LEN); |
| 51 | |
| 52 | for (size_t i = 1; i < ARRAY_SIZE(spdi->addresses); i++) { |
| 53 | if (spdi->addresses[i] == SPD_MEMORY_DOWN) |
| 54 | memcpy(pei_data->spd_data[i], pei_data->spd_data[0], SPD_LEN); |
| 55 | } |
Angel Pons | 6eea191 | 2020-07-03 14:14:30 +0200 | [diff] [blame] | 56 | } |
| 57 | |
Angel Pons | 73fa035 | 2020-07-03 12:29:03 +0200 | [diff] [blame] | 58 | void __weak mb_late_romstage_setup(void) |
| 59 | { |
| 60 | } |
| 61 | |
Angel Pons | d7bf3ad | 2020-07-03 20:31:39 +0200 | [diff] [blame] | 62 | /* |
| 63 | * 0 = leave channel enabled |
| 64 | * 1 = disable dimm 0 on channel |
| 65 | * 2 = disable dimm 1 on channel |
| 66 | * 3 = disable dimm 0+1 on channel |
| 67 | */ |
| 68 | static int make_channel_disabled_mask(const struct pei_data *pd, int ch) |
| 69 | { |
| 70 | return (!pd->spd_addresses[ch + ch] << 0) | (!pd->spd_addresses[ch + ch + 1] << 1); |
| 71 | } |
| 72 | |
Angel Pons | 45f448f | 2020-07-03 14:46:47 +0200 | [diff] [blame] | 73 | /* The romstage entry point for this platform is not mainboard-specific, hence the name */ |
| 74 | void mainboard_romstage_entry(void) |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 75 | { |
Angel Pons | 39a6093 | 2020-07-04 01:07:24 +0200 | [diff] [blame] | 76 | const struct device *gbe = pcidev_on_root(0x19, 0); |
| 77 | |
Angel Pons | 8aab787 | 2020-07-04 01:24:59 +0200 | [diff] [blame] | 78 | const struct northbridge_intel_haswell_config *cfg = config_of_soc(); |
| 79 | |
Angel Pons | 45f448f | 2020-07-03 14:46:47 +0200 | [diff] [blame] | 80 | struct pei_data pei_data = { |
Angel Pons | ae0eeb2 | 2020-07-04 01:38:03 +0200 | [diff] [blame] | 81 | .pei_version = PEI_VERSION, |
Angel Pons | f95b9b4 | 2021-01-20 01:10:48 +0100 | [diff] [blame] | 82 | .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, |
| 83 | .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, |
| 84 | .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, |
Angel Pons | ae0eeb2 | 2020-07-04 01:38:03 +0200 | [diff] [blame] | 85 | .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, |
Angel Pons | b21bffa | 2020-07-03 01:02:28 +0200 | [diff] [blame] | 86 | .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, |
Angel Pons | 0b39379 | 2021-03-12 12:54:45 +0100 | [diff] [blame] | 87 | .hpet_address = CONFIG_HPET_ADDRESS, |
Angel Pons | 6e732d3 | 2021-01-28 13:56:18 +0100 | [diff] [blame] | 88 | .rcba = CONFIG_FIXED_RCBA_MMIO_BASE, |
Angel Pons | ae0eeb2 | 2020-07-04 01:38:03 +0200 | [diff] [blame] | 89 | .pmbase = DEFAULT_PMBASE, |
| 90 | .gpiobase = DEFAULT_GPIOBASE, |
| 91 | .temp_mmio_base = 0xfed08000, |
| 92 | .system_type = get_pch_platform_type(), |
| 93 | .tseg_size = CONFIG_SMM_TSEG_SIZE, |
| 94 | .ec_present = cfg->ec_present, |
| 95 | .gbe_enable = gbe && gbe->enabled, |
| 96 | .ddr_refresh_2x = CONFIG(ENABLE_DDR_2X_REFRESH), |
| 97 | .dq_pins_interleaved = cfg->dq_pins_interleaved, |
| 98 | .max_ddr3_freq = 1600, |
| 99 | .usb_xhci_on_resume = cfg->usb_xhci_on_resume, |
Angel Pons | 45f448f | 2020-07-03 14:46:47 +0200 | [diff] [blame] | 100 | }; |
| 101 | |
Angel Pons | 33b59c9 | 2021-02-11 13:42:20 +0100 | [diff] [blame] | 102 | memcpy(pei_data.usb2_ports, mainboard_usb2_ports, sizeof(mainboard_usb2_ports)); |
| 103 | memcpy(pei_data.usb3_ports, mainboard_usb3_ports, sizeof(mainboard_usb3_ports)); |
Angel Pons | 45f448f | 2020-07-03 14:46:47 +0200 | [diff] [blame] | 104 | |
Kyösti Mälkki | 157b189 | 2019-08-16 14:02:25 +0300 | [diff] [blame] | 105 | enable_lapic(); |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 106 | |
Angel Pons | 30931f5 | 2021-03-12 13:06:45 +0100 | [diff] [blame] | 107 | early_pch_init(); |
| 108 | |
| 109 | const int s3resume = southbridge_detect_s3_resume(); |
| 110 | |
| 111 | elog_boot_notify(s3resume); |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 112 | |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 113 | /* Perform some early chipset initialization required |
| 114 | * before RAM initialization can work |
| 115 | */ |
Angel Pons | e816829 | 2020-07-03 11:42:22 +0200 | [diff] [blame] | 116 | haswell_early_initialization(); |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 117 | printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n"); |
| 118 | |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 119 | /* Prepare USB controller early in S3 resume */ |
Kyösti Mälkki | b6fc13b | 2021-02-17 17:33:09 +0200 | [diff] [blame] | 120 | if (s3resume) |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 121 | enable_usb_bar(); |
| 122 | |
| 123 | post_code(0x3a); |
Angel Pons | 284a547 | 2020-07-03 11:46:50 +0200 | [diff] [blame] | 124 | |
| 125 | /* MRC has hardcoded assumptions of 2 meaning S3 wake. Normalize it here. */ |
Kyösti Mälkki | b6fc13b | 2021-02-17 17:33:09 +0200 | [diff] [blame] | 126 | pei_data.boot_mode = s3resume ? 2 : 0; |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 127 | |
Angel Pons | d37b7d8 | 2020-07-03 23:52:34 +0200 | [diff] [blame] | 128 | /* Obtain the SPD addresses from mainboard code */ |
Angel Pons | 90ae089 | 2021-03-12 17:00:52 +0100 | [diff] [blame] | 129 | struct spd_info spdi = {0}; |
| 130 | mb_get_spd_map(&spdi); |
| 131 | |
| 132 | for (size_t i = 0; i < ARRAY_SIZE(spdi.addresses); i++) |
| 133 | pei_data.spd_addresses[i] = spdi.addresses[i]; |
Angel Pons | d37b7d8 | 2020-07-03 23:52:34 +0200 | [diff] [blame] | 134 | |
Angel Pons | d7bf3ad | 2020-07-03 20:31:39 +0200 | [diff] [blame] | 135 | /* Calculate unimplemented DIMM slots for each channel */ |
| 136 | pei_data.dimm_channel0_disabled = make_channel_disabled_mask(&pei_data, 0); |
| 137 | pei_data.dimm_channel1_disabled = make_channel_disabled_mask(&pei_data, 1); |
| 138 | |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 139 | timestamp_add_now(TS_BEFORE_INITRAM); |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 140 | |
| 141 | report_platform_info(); |
| 142 | |
Angel Pons | 6c49f40 | 2020-08-28 02:02:00 +0200 | [diff] [blame] | 143 | if (CONFIG(INTEL_TXT)) |
| 144 | intel_txt_romstage_init(); |
| 145 | |
Angel Pons | 90ae089 | 2021-03-12 17:00:52 +0100 | [diff] [blame] | 146 | copy_spd(&pei_data, &spdi); |
Aaron Durbin | c7633f4 | 2013-06-13 17:29:36 -0700 | [diff] [blame] | 147 | |
Angel Pons | 45f448f | 2020-07-03 14:46:47 +0200 | [diff] [blame] | 148 | sdram_initialize(&pei_data); |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 149 | |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 150 | timestamp_add_now(TS_AFTER_INITRAM); |
| 151 | |
Angel Pons | 6c49f40 | 2020-08-28 02:02:00 +0200 | [diff] [blame] | 152 | if (CONFIG(INTEL_TXT)) { |
| 153 | printk(BIOS_DEBUG, "Check TXT_ERROR register after MRC\n"); |
| 154 | |
| 155 | intel_txt_log_acm_error(read32((void *)TXT_ERROR)); |
| 156 | |
| 157 | intel_txt_log_spad(); |
| 158 | |
| 159 | intel_txt_memory_has_secrets(); |
| 160 | |
| 161 | txt_dump_regions(); |
| 162 | } |
| 163 | |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 164 | post_code(0x3b); |
| 165 | |
| 166 | intel_early_me_status(); |
| 167 | |
Kyösti Mälkki | b6fc13b | 2021-02-17 17:33:09 +0200 | [diff] [blame] | 168 | int cbmem_was_initted = !cbmem_recovery(s3resume); |
| 169 | if (s3resume && !cbmem_was_initted) { |
Aaron Durbin | 42e6856 | 2015-06-09 13:55:51 -0500 | [diff] [blame] | 170 | /* Failed S3 resume, reset to come up cleanly */ |
Kyösti Mälkki | b6fc13b | 2021-02-17 17:33:09 +0200 | [diff] [blame] | 171 | printk(BIOS_CRIT, "Failed to recover CBMEM in S3 resume.\n"); |
Patrick Rudolph | 45022ae | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 172 | system_reset(); |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 173 | } |
Aaron Durbin | bf396ff | 2013-02-11 21:50:35 -0600 | [diff] [blame] | 174 | |
Kyösti Mälkki | b6fc13b | 2021-02-17 17:33:09 +0200 | [diff] [blame] | 175 | /* Save data returned from MRC on non-S3 resumes. */ |
| 176 | if (!s3resume) |
| 177 | save_mrc_data(&pei_data); |
| 178 | |
| 179 | |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 180 | haswell_unhide_peg(); |
| 181 | |
Angel Pons | 45f448f | 2020-07-03 14:46:47 +0200 | [diff] [blame] | 182 | setup_sdram_meminfo(&pei_data); |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 183 | |
Kyösti Mälkki | b6fc13b | 2021-02-17 17:33:09 +0200 | [diff] [blame] | 184 | romstage_handoff_init(s3resume); |
Aaron Durbin | bf396ff | 2013-02-11 21:50:35 -0600 | [diff] [blame] | 185 | |
Angel Pons | 73fa035 | 2020-07-03 12:29:03 +0200 | [diff] [blame] | 186 | mb_late_romstage_setup(); |
| 187 | |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 188 | post_code(0x3f); |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 189 | } |