commit ae0eeb2ab6038c9f8aaaef119c5a51395b401168
author Angel Pons <th3fanbus@gmail.com> Sat Jul 04 01:38:03 2020 +0200
committer Angel Pons <th3fanbus@gmail.com> Sun Jul 12 11:16:37 2020 +0000
tree 4fa3882d1751638002703f04ba997bf9d593fd5a
parent 8aab7876d186ed9a8e978ec06a83a46f74a6179b

nb/intel/haswell/romstage.c: Align pei_data initializers

Aligned initializers should be easier to read.

Change-Id: If9238177c4959d80444fc842fd83794bfdac5c4b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Michael Niewöhner

src/northbridge/intel/haswell/romstage.c

diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c
index dfadad2..39babf5 100644
--- a/src/northbridge/intel/haswell/romstage.c
+++ b/src/northbridge/intel/haswell/romstage.c
@@ -46,25 +46,25 @@
 	int wake_from_s3;
 
 	struct pei_data pei_data = {
-		.pei_version = PEI_VERSION,
-		.mchbar = (uintptr_t)DEFAULT_MCHBAR,
-		.dmibar = (uintptr_t)DEFAULT_DMIBAR,
-		.epbar = DEFAULT_EPBAR,
-		.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
-		.smbusbar = SMBUS_IO_BASE,
-		.hpet_address = HPET_ADDR,
-		.rcba = (uintptr_t)DEFAULT_RCBA,
-		.pmbase = DEFAULT_PMBASE,
-		.gpiobase = DEFAULT_GPIOBASE,
-		.temp_mmio_base = 0xfed08000,
-		.system_type = get_pch_platform_type(),
-		.tseg_size = CONFIG_SMM_TSEG_SIZE,
-		.ec_present = cfg->ec_present,
-		.gbe_enable = gbe && gbe->enabled,
-		.ddr_refresh_2x = CONFIG(ENABLE_DDR_2X_REFRESH),
-		.dq_pins_interleaved = cfg->dq_pins_interleaved,
-		.max_ddr3_freq = 1600,
-		.usb_xhci_on_resume = cfg->usb_xhci_on_resume,
+		.pei_version		= PEI_VERSION,
+		.mchbar			= (uintptr_t)DEFAULT_MCHBAR,
+		.dmibar			= (uintptr_t)DEFAULT_DMIBAR,
+		.epbar			= DEFAULT_EPBAR,
+		.pciexbar		= CONFIG_MMCONF_BASE_ADDRESS,
+		.smbusbar		= SMBUS_IO_BASE,
+		.hpet_address		= HPET_ADDR,
+		.rcba			= (uintptr_t)DEFAULT_RCBA,
+		.pmbase			= DEFAULT_PMBASE,
+		.gpiobase		= DEFAULT_GPIOBASE,
+		.temp_mmio_base		= 0xfed08000,
+		.system_type		= get_pch_platform_type(),
+		.tseg_size		= CONFIG_SMM_TSEG_SIZE,
+		.ec_present		= cfg->ec_present,
+		.gbe_enable		= gbe && gbe->enabled,
+		.ddr_refresh_2x		= CONFIG(ENABLE_DDR_2X_REFRESH),
+		.dq_pins_interleaved	= cfg->dq_pins_interleaved,
+		.max_ddr3_freq		= 1600,
+		.usb_xhci_on_resume	= cfg->usb_xhci_on_resume,
 	};
 
 	mainboard_fill_pei_data(&pei_data);