Angel Pons | f23ae0b | 2020-04-02 23:48:12 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 2 | |
Angel Pons | 45f448f | 2020-07-03 14:46:47 +0200 | [diff] [blame] | 3 | #include <arch/romstage.h> |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 4 | #include <console/console.h> |
Patrick Rudolph | 45022ae | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 5 | #include <cf9_reset.h> |
Angel Pons | 39a6093 | 2020-07-04 01:07:24 +0200 | [diff] [blame] | 6 | #include <device/device.h> |
Angel Pons | 6c49f40 | 2020-08-28 02:02:00 +0200 | [diff] [blame] | 7 | #include <device/mmio.h> |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 8 | #include <timestamp.h> |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 9 | #include <cpu/x86/lapic.h> |
Kyösti Mälkki | 465eff6 | 2016-06-15 06:07:55 +0300 | [diff] [blame] | 10 | #include <cbmem.h> |
Elyes HAOUAS | d26844c | 2019-06-21 07:31:40 +0200 | [diff] [blame] | 11 | #include <commonlib/helpers.h> |
Aaron Durbin | bf396ff | 2013-02-11 21:50:35 -0600 | [diff] [blame] | 12 | #include <romstage_handoff.h> |
Angel Pons | 6c49f40 | 2020-08-28 02:02:00 +0200 | [diff] [blame] | 13 | #include <security/intel/txt/txt.h> |
| 14 | #include <security/intel/txt/txt_register.h> |
Angel Pons | 2e25ac6 | 2020-07-03 12:06:04 +0200 | [diff] [blame] | 15 | #include <cpu/intel/haswell/haswell.h> |
Angel Pons | 8aab787 | 2020-07-04 01:24:59 +0200 | [diff] [blame] | 16 | #include <northbridge/intel/haswell/chip.h> |
Elyes HAOUAS | 65bb543 | 2018-07-03 14:59:50 +0200 | [diff] [blame] | 17 | #include <northbridge/intel/haswell/haswell.h> |
| 18 | #include <northbridge/intel/haswell/raminit.h> |
| 19 | #include <southbridge/intel/lynxpoint/pch.h> |
| 20 | #include <southbridge/intel/lynxpoint/me.h> |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 21 | |
Angel Pons | 6eea191 | 2020-07-03 14:14:30 +0200 | [diff] [blame] | 22 | /* Copy SPD data for on-board memory */ |
| 23 | void __weak copy_spd(struct pei_data *peid) |
| 24 | { |
| 25 | } |
| 26 | |
Angel Pons | 73fa035 | 2020-07-03 12:29:03 +0200 | [diff] [blame] | 27 | void __weak mb_late_romstage_setup(void) |
| 28 | { |
| 29 | } |
| 30 | |
Angel Pons | d7bf3ad | 2020-07-03 20:31:39 +0200 | [diff] [blame] | 31 | /* |
| 32 | * 0 = leave channel enabled |
| 33 | * 1 = disable dimm 0 on channel |
| 34 | * 2 = disable dimm 1 on channel |
| 35 | * 3 = disable dimm 0+1 on channel |
| 36 | */ |
| 37 | static int make_channel_disabled_mask(const struct pei_data *pd, int ch) |
| 38 | { |
| 39 | return (!pd->spd_addresses[ch + ch] << 0) | (!pd->spd_addresses[ch + ch + 1] << 1); |
| 40 | } |
| 41 | |
Angel Pons | 45f448f | 2020-07-03 14:46:47 +0200 | [diff] [blame] | 42 | /* The romstage entry point for this platform is not mainboard-specific, hence the name */ |
| 43 | void mainboard_romstage_entry(void) |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 44 | { |
Angel Pons | 39a6093 | 2020-07-04 01:07:24 +0200 | [diff] [blame] | 45 | const struct device *gbe = pcidev_on_root(0x19, 0); |
| 46 | |
Angel Pons | 8aab787 | 2020-07-04 01:24:59 +0200 | [diff] [blame] | 47 | const struct northbridge_intel_haswell_config *cfg = config_of_soc(); |
| 48 | |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 49 | int wake_from_s3; |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 50 | |
Angel Pons | 45f448f | 2020-07-03 14:46:47 +0200 | [diff] [blame] | 51 | struct pei_data pei_data = { |
Angel Pons | ae0eeb2 | 2020-07-04 01:38:03 +0200 | [diff] [blame] | 52 | .pei_version = PEI_VERSION, |
| 53 | .mchbar = (uintptr_t)DEFAULT_MCHBAR, |
| 54 | .dmibar = (uintptr_t)DEFAULT_DMIBAR, |
| 55 | .epbar = DEFAULT_EPBAR, |
| 56 | .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, |
Angel Pons | b21bffa | 2020-07-03 01:02:28 +0200 | [diff] [blame] | 57 | .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, |
Angel Pons | ae0eeb2 | 2020-07-04 01:38:03 +0200 | [diff] [blame] | 58 | .hpet_address = HPET_ADDR, |
Angel Pons | 6e732d3 | 2021-01-28 13:56:18 +0100 | [diff] [blame^] | 59 | .rcba = CONFIG_FIXED_RCBA_MMIO_BASE, |
Angel Pons | ae0eeb2 | 2020-07-04 01:38:03 +0200 | [diff] [blame] | 60 | .pmbase = DEFAULT_PMBASE, |
| 61 | .gpiobase = DEFAULT_GPIOBASE, |
| 62 | .temp_mmio_base = 0xfed08000, |
| 63 | .system_type = get_pch_platform_type(), |
| 64 | .tseg_size = CONFIG_SMM_TSEG_SIZE, |
| 65 | .ec_present = cfg->ec_present, |
| 66 | .gbe_enable = gbe && gbe->enabled, |
| 67 | .ddr_refresh_2x = CONFIG(ENABLE_DDR_2X_REFRESH), |
| 68 | .dq_pins_interleaved = cfg->dq_pins_interleaved, |
| 69 | .max_ddr3_freq = 1600, |
| 70 | .usb_xhci_on_resume = cfg->usb_xhci_on_resume, |
Angel Pons | 45f448f | 2020-07-03 14:46:47 +0200 | [diff] [blame] | 71 | }; |
| 72 | |
| 73 | mainboard_fill_pei_data(&pei_data); |
| 74 | |
Kyösti Mälkki | 157b189 | 2019-08-16 14:02:25 +0300 | [diff] [blame] | 75 | enable_lapic(); |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 76 | |
Angel Pons | 03f0e43 | 2020-07-03 13:51:15 +0200 | [diff] [blame] | 77 | wake_from_s3 = early_pch_init(); |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 78 | |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 79 | /* Perform some early chipset initialization required |
| 80 | * before RAM initialization can work |
| 81 | */ |
Angel Pons | e816829 | 2020-07-03 11:42:22 +0200 | [diff] [blame] | 82 | haswell_early_initialization(); |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 83 | printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n"); |
| 84 | |
| 85 | if (wake_from_s3) { |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 86 | #if CONFIG(HAVE_ACPI_RESUME) |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 87 | printk(BIOS_DEBUG, "Resume from S3 detected.\n"); |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 88 | #else |
| 89 | printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); |
Aaron Durbin | bf396ff | 2013-02-11 21:50:35 -0600 | [diff] [blame] | 90 | wake_from_s3 = 0; |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 91 | #endif |
| 92 | } |
| 93 | |
| 94 | /* Prepare USB controller early in S3 resume */ |
Aaron Durbin | bf396ff | 2013-02-11 21:50:35 -0600 | [diff] [blame] | 95 | if (wake_from_s3) |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 96 | enable_usb_bar(); |
| 97 | |
| 98 | post_code(0x3a); |
Angel Pons | 284a547 | 2020-07-03 11:46:50 +0200 | [diff] [blame] | 99 | |
| 100 | /* MRC has hardcoded assumptions of 2 meaning S3 wake. Normalize it here. */ |
Angel Pons | 45f448f | 2020-07-03 14:46:47 +0200 | [diff] [blame] | 101 | pei_data.boot_mode = wake_from_s3 ? 2 : 0; |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 102 | |
Angel Pons | d37b7d8 | 2020-07-03 23:52:34 +0200 | [diff] [blame] | 103 | /* Obtain the SPD addresses from mainboard code */ |
| 104 | mb_get_spd_map(pei_data.spd_addresses); |
| 105 | |
Angel Pons | d7bf3ad | 2020-07-03 20:31:39 +0200 | [diff] [blame] | 106 | /* Calculate unimplemented DIMM slots for each channel */ |
| 107 | pei_data.dimm_channel0_disabled = make_channel_disabled_mask(&pei_data, 0); |
| 108 | pei_data.dimm_channel1_disabled = make_channel_disabled_mask(&pei_data, 1); |
| 109 | |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 110 | timestamp_add_now(TS_BEFORE_INITRAM); |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 111 | |
| 112 | report_platform_info(); |
| 113 | |
Angel Pons | 6c49f40 | 2020-08-28 02:02:00 +0200 | [diff] [blame] | 114 | if (CONFIG(INTEL_TXT)) |
| 115 | intel_txt_romstage_init(); |
| 116 | |
Angel Pons | 45f448f | 2020-07-03 14:46:47 +0200 | [diff] [blame] | 117 | copy_spd(&pei_data); |
Aaron Durbin | c7633f4 | 2013-06-13 17:29:36 -0700 | [diff] [blame] | 118 | |
Angel Pons | 45f448f | 2020-07-03 14:46:47 +0200 | [diff] [blame] | 119 | sdram_initialize(&pei_data); |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 120 | |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 121 | timestamp_add_now(TS_AFTER_INITRAM); |
| 122 | |
Angel Pons | 6c49f40 | 2020-08-28 02:02:00 +0200 | [diff] [blame] | 123 | if (CONFIG(INTEL_TXT)) { |
| 124 | printk(BIOS_DEBUG, "Check TXT_ERROR register after MRC\n"); |
| 125 | |
| 126 | intel_txt_log_acm_error(read32((void *)TXT_ERROR)); |
| 127 | |
| 128 | intel_txt_log_spad(); |
| 129 | |
| 130 | intel_txt_memory_has_secrets(); |
| 131 | |
| 132 | txt_dump_regions(); |
| 133 | } |
| 134 | |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 135 | post_code(0x3b); |
| 136 | |
| 137 | intel_early_me_status(); |
| 138 | |
Aaron Durbin | c0cbd6e | 2013-03-13 13:51:20 -0500 | [diff] [blame] | 139 | if (!wake_from_s3) { |
| 140 | cbmem_initialize_empty(); |
| 141 | /* Save data returned from MRC on non-S3 resumes. */ |
Angel Pons | 45f448f | 2020-07-03 14:46:47 +0200 | [diff] [blame] | 142 | save_mrc_data(&pei_data); |
Aaron Durbin | 42e6856 | 2015-06-09 13:55:51 -0500 | [diff] [blame] | 143 | } else if (cbmem_initialize()) { |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 144 | #if CONFIG(HAVE_ACPI_RESUME) |
Aaron Durbin | 42e6856 | 2015-06-09 13:55:51 -0500 | [diff] [blame] | 145 | /* Failed S3 resume, reset to come up cleanly */ |
Patrick Rudolph | 45022ae | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 146 | system_reset(); |
Aaron Durbin | 42e6856 | 2015-06-09 13:55:51 -0500 | [diff] [blame] | 147 | #endif |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 148 | } |
Aaron Durbin | bf396ff | 2013-02-11 21:50:35 -0600 | [diff] [blame] | 149 | |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 150 | haswell_unhide_peg(); |
| 151 | |
Angel Pons | 45f448f | 2020-07-03 14:46:47 +0200 | [diff] [blame] | 152 | setup_sdram_meminfo(&pei_data); |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 153 | |
Aaron Durbin | 77e1399 | 2016-11-29 17:43:04 -0600 | [diff] [blame] | 154 | romstage_handoff_init(wake_from_s3); |
Aaron Durbin | bf396ff | 2013-02-11 21:50:35 -0600 | [diff] [blame] | 155 | |
Angel Pons | 73fa035 | 2020-07-03 12:29:03 +0200 | [diff] [blame] | 156 | mb_late_romstage_setup(); |
| 157 | |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 158 | post_code(0x3f); |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 159 | } |