haswell: Automatically check if Intel GbE is to be enabled
If the Intel in-PCH GbE MAC is enabled in the devicetree, then tell MRC
to enable it as well. No one can ever forget to set this option anymore!
Change-Id: I946af36d16c94bb1a0f146604d0329fe6d6ce7e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43128
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c
index 2961299..7016fd9 100644
--- a/src/northbridge/intel/haswell/romstage.c
+++ b/src/northbridge/intel/haswell/romstage.c
@@ -3,6 +3,7 @@
#include <arch/romstage.h>
#include <console/console.h>
#include <cf9_reset.h>
+#include <device/device.h>
#include <timestamp.h>
#include <cpu/x86/lapic.h>
#include <cbmem.h>
@@ -37,6 +38,8 @@
/* The romstage entry point for this platform is not mainboard-specific, hence the name */
void mainboard_romstage_entry(void)
{
+ const struct device *gbe = pcidev_on_root(0x19, 0);
+
int wake_from_s3;
struct pei_data pei_data = {
@@ -53,6 +56,7 @@
.temp_mmio_base = 0xfed08000,
.system_type = get_pch_platform_type(),
.tseg_size = CONFIG_SMM_TSEG_SIZE,
+ .gbe_enable = gbe && gbe->enabled,
.ddr_refresh_2x = CONFIG(ENABLE_DDR_2X_REFRESH),
.max_ddr3_freq = 1600,
};