Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 ChromeOS Authors |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <stdint.h> |
| 21 | #include <cbmem.h> |
| 22 | #include <console/console.h> |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame^] | 23 | #include <arch/cpu.h> |
| 24 | #include <cpu/x86/bist.h> |
| 25 | #include <cpu/x86/msr.h> |
| 26 | #include <lib.h> |
| 27 | #include <timestamp.h> |
| 28 | #include <arch/io.h> |
| 29 | #include <arch/romcc_io.h> |
| 30 | #include <device/pci_def.h> |
| 31 | #include <cpu/x86/lapic.h> |
| 32 | #include <cbmem.h> |
| 33 | #if CONFIG_CHROMEOS |
| 34 | #include <vendorcode/google/chromeos/chromeos.h> |
| 35 | #endif |
| 36 | #include "haswell.h" |
| 37 | #include "northbridge/intel/haswell/haswell.h" |
| 38 | #include "northbridge/intel/haswell/raminit.h" |
| 39 | #include "southbridge/intel/lynxpoint/pch.h" |
| 40 | #include "southbridge/intel/lynxpoint/me.h" |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 41 | |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame^] | 42 | |
| 43 | /* The cache-as-ram assembly file calls main() after setting up cache-as-ram. |
| 44 | * main() will then call the mainboards's mainboard_romstage_entry() function. |
| 45 | * That function then calls romstage_common() below. The reason for the back |
| 46 | * and forth is to provide common entry point from cache-as-ram while still |
| 47 | * allowing for code sharing. Because we can't use global variables the stack |
| 48 | * is used for allocations -- thus the need to call back and forth. */ |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 49 | |
| 50 | void main(unsigned long bist) |
| 51 | { |
| 52 | int i; |
| 53 | const int num_guards = 4; |
| 54 | const u32 stack_guard = 0xdeadbeef; |
| 55 | u32 *stack_base = (void *)(CONFIG_DCACHE_RAM_BASE + |
| 56 | CONFIG_DCACHE_RAM_SIZE - |
| 57 | CONFIG_DCACHE_RAM_ROMSTAGE_STACK_SIZE); |
| 58 | |
| 59 | printk(BIOS_DEBUG, "Setting up stack guards.\n"); |
| 60 | for (i = 0; i < num_guards; i++) |
| 61 | stack_base[i] = stack_guard; |
| 62 | |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame^] | 63 | mainboard_romstage_entry(bist); |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 64 | |
| 65 | /* Check the stack. */ |
| 66 | for (i = 0; i < num_guards; i++) { |
| 67 | if (stack_base[i] == stack_guard) |
| 68 | continue; |
| 69 | printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n"); |
| 70 | } |
| 71 | |
| 72 | #if CONFIG_CONSOLE_CBMEM |
| 73 | /* Keep this the last thing this function does. */ |
| 74 | cbmemc_reinit(); |
| 75 | #endif |
| 76 | } |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame^] | 77 | |
| 78 | void romstage_common(const struct romstage_params *params) |
| 79 | { |
| 80 | int boot_mode = 0; |
| 81 | int wake_from_s3; |
| 82 | int cbmem_was_initted; |
| 83 | |
| 84 | #if CONFIG_COLLECT_TIMESTAMPS |
| 85 | tsc_t start_romstage_time; |
| 86 | tsc_t before_dram_time; |
| 87 | tsc_t after_dram_time; |
| 88 | tsc_t base_time = { |
| 89 | .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), |
| 90 | .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) |
| 91 | }; |
| 92 | #endif |
| 93 | |
| 94 | #if CONFIG_COLLECT_TIMESTAMPS |
| 95 | start_romstage_time = rdtsc(); |
| 96 | #endif |
| 97 | |
| 98 | if (params->bist == 0) |
| 99 | enable_lapic(); |
| 100 | |
| 101 | wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config); |
| 102 | |
| 103 | /* Halt if there was a built in self test failure */ |
| 104 | report_bist_failure(params->bist); |
| 105 | |
| 106 | /* Perform some early chipset initialization required |
| 107 | * before RAM initialization can work |
| 108 | */ |
| 109 | haswell_early_initialization(HASWELL_MOBILE); |
| 110 | printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n"); |
| 111 | |
| 112 | if (wake_from_s3) { |
| 113 | #if CONFIG_HAVE_ACPI_RESUME |
| 114 | printk(BIOS_DEBUG, "Resume from S3 detected.\n"); |
| 115 | boot_mode = 2; |
| 116 | #else |
| 117 | printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); |
| 118 | #endif |
| 119 | } |
| 120 | |
| 121 | /* Prepare USB controller early in S3 resume */ |
| 122 | if (boot_mode == 2) |
| 123 | enable_usb_bar(); |
| 124 | |
| 125 | post_code(0x3a); |
| 126 | params->pei_data->boot_mode = boot_mode; |
| 127 | #if CONFIG_COLLECT_TIMESTAMPS |
| 128 | before_dram_time = rdtsc(); |
| 129 | #endif |
| 130 | |
| 131 | report_platform_info(); |
| 132 | |
| 133 | sdram_initialize(params->pei_data); |
| 134 | |
| 135 | #if CONFIG_COLLECT_TIMESTAMPS |
| 136 | after_dram_time = rdtsc(); |
| 137 | #endif |
| 138 | post_code(0x3b); |
| 139 | |
| 140 | intel_early_me_status(); |
| 141 | |
| 142 | quick_ram_check(); |
| 143 | post_code(0x3e); |
| 144 | |
| 145 | #if CONFIG_EARLY_CBMEM_INIT |
| 146 | cbmem_was_initted = !cbmem_initialize(); |
| 147 | #else |
| 148 | cbmem_was_initted = cbmem_reinit((uint64_t) (get_top_of_ram() |
| 149 | - HIGH_MEMORY_SIZE)); |
| 150 | #endif |
| 151 | |
| 152 | #if CONFIG_HAVE_ACPI_RESUME |
| 153 | /* If there is no high memory area, we didn't boot before, so |
| 154 | * this is not a resume. In that case we just create the cbmem toc. |
| 155 | */ |
| 156 | |
| 157 | *(u32 *)CBMEM_BOOT_MODE = 0; |
| 158 | *(u32 *)CBMEM_RESUME_BACKUP = 0; |
| 159 | |
| 160 | if ((boot_mode == 2) && cbmem_was_initted) { |
| 161 | void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); |
| 162 | if (resume_backup_memory) { |
| 163 | *(u32 *)CBMEM_BOOT_MODE = boot_mode; |
| 164 | *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; |
| 165 | } |
| 166 | /* Magic for S3 resume */ |
| 167 | pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); |
| 168 | } else if (boot_mode == 2) { |
| 169 | /* Failed S3 resume, reset to come up cleanly */ |
| 170 | outb(0x6, 0xcf9); |
| 171 | while (1) { |
| 172 | hlt(); |
| 173 | } |
| 174 | } else { |
| 175 | pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); |
| 176 | } |
| 177 | #endif |
| 178 | post_code(0x3f); |
| 179 | #if CONFIG_CHROMEOS |
| 180 | init_chromeos(boot_mode); |
| 181 | #endif |
| 182 | #if CONFIG_COLLECT_TIMESTAMPS |
| 183 | timestamp_init(base_time); |
| 184 | timestamp_add(TS_START_ROMSTAGE, start_romstage_time ); |
| 185 | timestamp_add(TS_BEFORE_INITRAM, before_dram_time ); |
| 186 | timestamp_add(TS_AFTER_INITRAM, after_dram_time ); |
| 187 | timestamp_add_now(TS_END_ROMSTAGE); |
| 188 | #endif |
| 189 | } |