Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Patrick Georgi | 5b2a2d0 | 2018-09-26 20:46:04 +0200 | [diff] [blame] | 4 | * Copyright (C) 2012 Google LLC |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <stdint.h> |
Aaron Durbin | 7492ec1 | 2013-02-08 22:18:04 -0600 | [diff] [blame] | 17 | #include <string.h> |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 18 | #include <console/console.h> |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 19 | #include <arch/cpu.h> |
Patrick Rudolph | 45022ae | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 20 | #include <cf9_reset.h> |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 21 | #include <cpu/x86/bist.h> |
| 22 | #include <cpu/x86/msr.h> |
Aaron Durbin | 38d9423 | 2013-02-07 00:03:33 -0600 | [diff] [blame] | 23 | #include <cpu/x86/mtrr.h> |
Patrick Georgi | bd79c5e | 2014-11-28 22:35:36 +0100 | [diff] [blame] | 24 | #include <halt.h> |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 25 | #include <lib.h> |
| 26 | #include <timestamp.h> |
Kyösti Mälkki | a969ed3 | 2016-06-15 06:08:15 +0300 | [diff] [blame] | 27 | #include <arch/acpi.h> |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 28 | #include <arch/io.h> |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 29 | #include <device/pci_def.h> |
| 30 | #include <cpu/x86/lapic.h> |
Kyösti Mälkki | 465eff6 | 2016-06-15 06:07:55 +0300 | [diff] [blame] | 31 | #include <cbmem.h> |
Kyösti Mälkki | 65e8f64 | 2016-06-27 11:27:56 +0300 | [diff] [blame] | 32 | #include <program_loading.h> |
Aaron Durbin | bf396ff | 2013-02-11 21:50:35 -0600 | [diff] [blame] | 33 | #include <romstage_handoff.h> |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 34 | #include <vendorcode/google/chromeos/chromeos.h> |
Martin Roth | ffdee28 | 2017-06-24 13:43:40 -0600 | [diff] [blame] | 35 | #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) |
Duncan Laurie | 7cced0d | 2013-06-04 10:03:34 -0700 | [diff] [blame] | 36 | #include <ec/google/chromeec/ec.h> |
| 37 | #endif |
Elyes HAOUAS | 65bb543 | 2018-07-03 14:59:50 +0200 | [diff] [blame] | 38 | #include <northbridge/intel/haswell/haswell.h> |
| 39 | #include <northbridge/intel/haswell/raminit.h> |
| 40 | #include <southbridge/intel/lynxpoint/pch.h> |
| 41 | #include <southbridge/intel/lynxpoint/me.h> |
Arthur Heymans | faa5f98 | 2018-06-04 19:34:59 +0200 | [diff] [blame] | 42 | #include <cpu/intel/romstage.h> |
Elyes HAOUAS | 65bb543 | 2018-07-03 14:59:50 +0200 | [diff] [blame] | 43 | #include "haswell.h" |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 44 | |
Arthur Heymans | 88af0f3 | 2018-06-03 12:37:54 +0200 | [diff] [blame] | 45 | #define ROMSTAGE_RAM_STACK_SIZE 0x5000 |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 46 | |
Arthur Heymans | 88af0f3 | 2018-06-03 12:37:54 +0200 | [diff] [blame] | 47 | /* platform_enter_postcar() determines the stack to use after |
| 48 | * cache-as-ram is torn down as well as the MTRR settings to use, |
| 49 | * and continues execution in postcar stage. */ |
Arthur Heymans | faa5f98 | 2018-06-04 19:34:59 +0200 | [diff] [blame] | 50 | void platform_enter_postcar(void) |
Aaron Durbin | 38d9423 | 2013-02-07 00:03:33 -0600 | [diff] [blame] | 51 | { |
Arthur Heymans | 88af0f3 | 2018-06-03 12:37:54 +0200 | [diff] [blame] | 52 | struct postcar_frame pcf; |
| 53 | uintptr_t top_of_ram; |
Aaron Durbin | 38d9423 | 2013-02-07 00:03:33 -0600 | [diff] [blame] | 54 | |
Arthur Heymans | 88af0f3 | 2018-06-03 12:37:54 +0200 | [diff] [blame] | 55 | if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) |
| 56 | die("Unable to initialize postcar frame.\n"); |
Aaron Durbin | 38d9423 | 2013-02-07 00:03:33 -0600 | [diff] [blame] | 57 | /* Cache the ROM as WP just below 4GiB. */ |
Arthur Heymans | 88af0f3 | 2018-06-03 12:37:54 +0200 | [diff] [blame] | 58 | postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, |
| 59 | MTRR_TYPE_WRPROT); |
Aaron Durbin | 38d9423 | 2013-02-07 00:03:33 -0600 | [diff] [blame] | 60 | |
Kyösti Mälkki | 65cc526 | 2016-06-19 20:38:41 +0300 | [diff] [blame] | 61 | /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ |
Arthur Heymans | 88af0f3 | 2018-06-03 12:37:54 +0200 | [diff] [blame] | 62 | postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); |
Aaron Durbin | 38d9423 | 2013-02-07 00:03:33 -0600 | [diff] [blame] | 63 | |
Arthur Heymans | 88af0f3 | 2018-06-03 12:37:54 +0200 | [diff] [blame] | 64 | /* Cache at least 8 MiB below the top of ram, and at most 8 MiB |
| 65 | * above top of the ram. This satisfies MTRR alignment requirement |
| 66 | * with different TSEG size configurations. |
| 67 | */ |
| 68 | top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); |
| 69 | postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB, |
| 70 | MTRR_TYPE_WRBACK); |
Aaron Durbin | 67481ddc | 2013-02-15 15:08:37 -0600 | [diff] [blame] | 71 | |
Arthur Heymans | 88af0f3 | 2018-06-03 12:37:54 +0200 | [diff] [blame] | 72 | run_postcar_phase(&pcf); |
Aaron Durbin | 38d9423 | 2013-02-07 00:03:33 -0600 | [diff] [blame] | 73 | } |
| 74 | |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 75 | void romstage_common(const struct romstage_params *params) |
| 76 | { |
Aaron Durbin | bf396ff | 2013-02-11 21:50:35 -0600 | [diff] [blame] | 77 | int boot_mode; |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 78 | int wake_from_s3; |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 79 | |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 80 | timestamp_init(get_initial_timestamp()); |
| 81 | timestamp_add_now(TS_START_ROMSTAGE); |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 82 | |
| 83 | if (params->bist == 0) |
| 84 | enable_lapic(); |
| 85 | |
| 86 | wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config); |
| 87 | |
| 88 | /* Halt if there was a built in self test failure */ |
| 89 | report_bist_failure(params->bist); |
| 90 | |
| 91 | /* Perform some early chipset initialization required |
| 92 | * before RAM initialization can work |
| 93 | */ |
| 94 | haswell_early_initialization(HASWELL_MOBILE); |
| 95 | printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n"); |
| 96 | |
| 97 | if (wake_from_s3) { |
Martin Roth | ffdee28 | 2017-06-24 13:43:40 -0600 | [diff] [blame] | 98 | #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 99 | printk(BIOS_DEBUG, "Resume from S3 detected.\n"); |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 100 | #else |
| 101 | printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); |
Aaron Durbin | bf396ff | 2013-02-11 21:50:35 -0600 | [diff] [blame] | 102 | wake_from_s3 = 0; |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 103 | #endif |
| 104 | } |
| 105 | |
Aaron Durbin | bf396ff | 2013-02-11 21:50:35 -0600 | [diff] [blame] | 106 | /* There are hard coded assumptions of 2 meaning s3 wake. Normalize |
| 107 | * the users of the 2 literal here based off wake_from_s3. */ |
| 108 | boot_mode = wake_from_s3 ? 2 : 0; |
| 109 | |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 110 | /* Prepare USB controller early in S3 resume */ |
Aaron Durbin | bf396ff | 2013-02-11 21:50:35 -0600 | [diff] [blame] | 111 | if (wake_from_s3) |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 112 | enable_usb_bar(); |
| 113 | |
| 114 | post_code(0x3a); |
| 115 | params->pei_data->boot_mode = boot_mode; |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 116 | |
| 117 | timestamp_add_now(TS_BEFORE_INITRAM); |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 118 | |
| 119 | report_platform_info(); |
| 120 | |
Aaron Durbin | c7633f4 | 2013-06-13 17:29:36 -0700 | [diff] [blame] | 121 | if (params->copy_spd != NULL) |
| 122 | params->copy_spd(params->pei_data); |
| 123 | |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 124 | sdram_initialize(params->pei_data); |
| 125 | |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 126 | timestamp_add_now(TS_AFTER_INITRAM); |
| 127 | |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 128 | post_code(0x3b); |
| 129 | |
| 130 | intel_early_me_status(); |
| 131 | |
| 132 | quick_ram_check(); |
| 133 | post_code(0x3e); |
| 134 | |
Aaron Durbin | c0cbd6e | 2013-03-13 13:51:20 -0500 | [diff] [blame] | 135 | if (!wake_from_s3) { |
| 136 | cbmem_initialize_empty(); |
| 137 | /* Save data returned from MRC on non-S3 resumes. */ |
Aaron Durbin | 2ad1dba | 2013-02-07 00:51:18 -0600 | [diff] [blame] | 138 | save_mrc_data(params->pei_data); |
Aaron Durbin | 42e6856 | 2015-06-09 13:55:51 -0500 | [diff] [blame] | 139 | } else if (cbmem_initialize()) { |
Martin Roth | ffdee28 | 2017-06-24 13:43:40 -0600 | [diff] [blame] | 140 | #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) |
Aaron Durbin | 42e6856 | 2015-06-09 13:55:51 -0500 | [diff] [blame] | 141 | /* Failed S3 resume, reset to come up cleanly */ |
Patrick Rudolph | 45022ae | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 142 | system_reset(); |
Aaron Durbin | 42e6856 | 2015-06-09 13:55:51 -0500 | [diff] [blame] | 143 | #endif |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 144 | } |
Aaron Durbin | bf396ff | 2013-02-11 21:50:35 -0600 | [diff] [blame] | 145 | |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame^] | 146 | haswell_unhide_peg(); |
| 147 | |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 148 | setup_sdram_meminfo(params->pei_data); |
| 149 | |
Aaron Durbin | 77e1399 | 2016-11-29 17:43:04 -0600 | [diff] [blame] | 150 | romstage_handoff_init(wake_from_s3); |
Aaron Durbin | bf396ff | 2013-02-11 21:50:35 -0600 | [diff] [blame] | 151 | |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 152 | post_code(0x3f); |
Aaron Durbin | a267161 | 2013-02-06 21:41:01 -0600 | [diff] [blame] | 153 | } |