Angel Pons | f23ae0b | 2020-04-02 23:48:12 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <device/device.h> |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 5 | #include <cpu/cpu.h> |
| 6 | #include <cpu/x86/mtrr.h> |
| 7 | #include <cpu/x86/msr.h> |
Arthur Heymans | edbf5d9 | 2018-01-25 20:03:42 +0100 | [diff] [blame] | 8 | #include <cpu/x86/mp.h> |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 9 | #include <cpu/intel/microcode.h> |
| 10 | #include <cpu/intel/speedstep.h> |
| 11 | #include <cpu/intel/turbo.h> |
| 12 | #include <cpu/x86/cache.h> |
| 13 | #include <cpu/x86/name.h> |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 14 | #include "model_206ax.h" |
Duncan Laurie | 5563211 | 2012-07-16 12:19:00 -0700 | [diff] [blame] | 15 | #include "chip.h" |
Kyösti Mälkki | f091f4d | 2019-08-14 03:49:21 +0300 | [diff] [blame] | 16 | #include <cpu/intel/smm_reloc.h> |
Matt DeVillier | ed6fe2f | 2016-12-14 16:12:43 -0600 | [diff] [blame] | 17 | #include <cpu/intel/common/common.h> |
Michał Żygowski | 0d11dbf | 2020-10-31 21:43:25 +0100 | [diff] [blame] | 18 | #include <smbios.h> |
Patrick Rudolph | ea04a53 | 2023-10-20 14:17:24 +0200 | [diff] [blame] | 19 | #include <smp/node.h> |
Felix Held | d27ef5b | 2021-10-20 20:18:12 +0200 | [diff] [blame] | 20 | #include <types.h> |
Vladimir Serbinenko | c16e9dfa | 2015-05-29 16:18:01 +0200 | [diff] [blame] | 21 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 22 | /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ |
| 23 | static const u8 power_limit_time_sec_to_msr[] = { |
| 24 | [0] = 0x00, |
| 25 | [1] = 0x0a, |
| 26 | [2] = 0x0b, |
| 27 | [3] = 0x4b, |
| 28 | [4] = 0x0c, |
| 29 | [5] = 0x2c, |
| 30 | [6] = 0x4c, |
| 31 | [7] = 0x6c, |
| 32 | [8] = 0x0d, |
| 33 | [10] = 0x2d, |
| 34 | [12] = 0x4d, |
| 35 | [14] = 0x6d, |
| 36 | [16] = 0x0e, |
| 37 | [20] = 0x2e, |
| 38 | [24] = 0x4e, |
| 39 | [28] = 0x6e, |
| 40 | [32] = 0x0f, |
| 41 | [40] = 0x2f, |
| 42 | [48] = 0x4f, |
| 43 | [56] = 0x6f, |
| 44 | [64] = 0x10, |
| 45 | [80] = 0x30, |
| 46 | [96] = 0x50, |
| 47 | [112] = 0x70, |
| 48 | [128] = 0x11, |
| 49 | }; |
| 50 | |
| 51 | /* Convert POWER_LIMIT_1_TIME MSR value to seconds */ |
| 52 | static const u8 power_limit_time_msr_to_sec[] = { |
| 53 | [0x00] = 0, |
| 54 | [0x0a] = 1, |
| 55 | [0x0b] = 2, |
| 56 | [0x4b] = 3, |
| 57 | [0x0c] = 4, |
| 58 | [0x2c] = 5, |
| 59 | [0x4c] = 6, |
| 60 | [0x6c] = 7, |
| 61 | [0x0d] = 8, |
| 62 | [0x2d] = 10, |
| 63 | [0x4d] = 12, |
| 64 | [0x6d] = 14, |
| 65 | [0x0e] = 16, |
| 66 | [0x2e] = 20, |
| 67 | [0x4e] = 24, |
| 68 | [0x6e] = 28, |
| 69 | [0x0f] = 32, |
| 70 | [0x2f] = 40, |
| 71 | [0x4f] = 48, |
| 72 | [0x6f] = 56, |
| 73 | [0x10] = 64, |
| 74 | [0x30] = 80, |
| 75 | [0x50] = 96, |
| 76 | [0x70] = 112, |
| 77 | [0x11] = 128, |
| 78 | }; |
| 79 | |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 80 | int cpu_config_tdp_levels(void) |
| 81 | { |
| 82 | msr_t platform_info; |
| 83 | |
| 84 | /* Minimum CPU revision */ |
| 85 | if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID) |
| 86 | return 0; |
| 87 | |
| 88 | /* Bits 34:33 indicate how many levels supported */ |
| 89 | platform_info = rdmsr(MSR_PLATFORM_INFO); |
| 90 | return (platform_info.hi >> 1) & 3; |
| 91 | } |
| 92 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 93 | /* |
| 94 | * Configure processor power limits if possible |
| 95 | * This must be done AFTER set of BIOS_RESET_CPL |
| 96 | */ |
| 97 | void set_power_limits(u8 power_limit_1_time) |
| 98 | { |
| 99 | msr_t msr = rdmsr(MSR_PLATFORM_INFO); |
| 100 | msr_t limit; |
Lee Leahy | 73a2894 | 2017-03-15 17:52:06 -0700 | [diff] [blame] | 101 | unsigned int power_unit; |
| 102 | unsigned int tdp, min_power, max_power, max_time; |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 103 | u8 power_limit_1_val; |
| 104 | |
Edward O'Callaghan | 5cfef13 | 2014-08-03 20:00:47 +1000 | [diff] [blame] | 105 | if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 106 | return; |
| 107 | |
| 108 | if (!(msr.lo & PLATFORM_INFO_SET_TDP)) |
| 109 | return; |
| 110 | |
| 111 | /* Get units */ |
| 112 | msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); |
| 113 | power_unit = 2 << ((msr.lo & 0xf) - 1); |
| 114 | |
| 115 | /* Get power defaults for this SKU */ |
| 116 | msr = rdmsr(MSR_PKG_POWER_SKU); |
| 117 | tdp = msr.lo & 0x7fff; |
| 118 | min_power = (msr.lo >> 16) & 0x7fff; |
| 119 | max_power = msr.hi & 0x7fff; |
| 120 | max_time = (msr.hi >> 16) & 0x7f; |
| 121 | |
| 122 | printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit); |
| 123 | |
| 124 | if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time) |
| 125 | power_limit_1_time = power_limit_time_msr_to_sec[max_time]; |
| 126 | |
| 127 | if (min_power > 0 && tdp < min_power) |
| 128 | tdp = min_power; |
| 129 | |
| 130 | if (max_power > 0 && tdp > max_power) |
| 131 | tdp = max_power; |
| 132 | |
| 133 | power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time]; |
| 134 | |
| 135 | /* Set long term power limit to TDP */ |
| 136 | limit.lo = 0; |
| 137 | limit.lo |= tdp & PKG_POWER_LIMIT_MASK; |
| 138 | limit.lo |= PKG_POWER_LIMIT_EN; |
| 139 | limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << |
| 140 | PKG_POWER_LIMIT_TIME_SHIFT; |
| 141 | |
| 142 | /* Set short term power limit to 1.25 * TDP */ |
| 143 | limit.hi = 0; |
| 144 | limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK; |
| 145 | limit.hi |= PKG_POWER_LIMIT_EN; |
| 146 | /* Power limit 2 time is only programmable on SNB EP/EX */ |
| 147 | |
| 148 | wrmsr(MSR_PKG_POWER_LIMIT, limit); |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 149 | |
| 150 | /* Use nominal TDP values for CPUs with configurable TDP */ |
| 151 | if (cpu_config_tdp_levels()) { |
| 152 | msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); |
| 153 | limit.hi = 0; |
| 154 | limit.lo = msr.lo & 0xff; |
| 155 | wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit); |
| 156 | } |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 157 | } |
| 158 | |
| 159 | static void configure_c_states(void) |
| 160 | { |
| 161 | msr_t msr; |
| 162 | |
Elyes HAOUAS | 4e6b790 | 2018-10-02 08:44:47 +0200 | [diff] [blame] | 163 | msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 164 | msr.lo |= (1 << 28); // C1 Auto Undemotion Enable |
| 165 | msr.lo |= (1 << 27); // C3 Auto Undemotion Enable |
| 166 | msr.lo |= (1 << 26); // C1 Auto Demotion Enable |
| 167 | msr.lo |= (1 << 25); // C3 Auto Demotion Enable |
| 168 | msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection |
| 169 | msr.lo |= 7; // No package C-state limit |
Patrick Rudolph | 573481b | 2020-03-02 14:21:32 +0100 | [diff] [blame] | 170 | |
| 171 | msr.lo |= (1 << 15); // Lock C-State MSR |
Elyes HAOUAS | 4e6b790 | 2018-10-02 08:44:47 +0200 | [diff] [blame] | 172 | wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 173 | |
Patrick Rudolph | ea04a53 | 2023-10-20 14:17:24 +0200 | [diff] [blame] | 174 | if (boot_cpu()) { |
| 175 | /* |
| 176 | * The following MSRs are in scope 'Package', thus it's sufficient |
| 177 | * to write them once on one core. |
| 178 | */ |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 179 | |
Patrick Rudolph | ea04a53 | 2023-10-20 14:17:24 +0200 | [diff] [blame] | 180 | msr = rdmsr(MSR_MISC_PWR_MGMT); |
| 181 | msr.lo &= ~(1 << 0); // Enable P-state HW_ALL coordination |
| 182 | wrmsr(MSR_MISC_PWR_MGMT, msr); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 183 | |
Patrick Rudolph | ea04a53 | 2023-10-20 14:17:24 +0200 | [diff] [blame] | 184 | msr = rdmsr(MSR_POWER_CTL); |
| 185 | msr.lo |= (1 << 18); // Enable Energy Perf Bias MSR 0x1b0 |
| 186 | msr.lo |= (1 << 1); // C1E Enable |
| 187 | msr.lo |= (1 << 0); // Bi-directional PROCHOT# |
| 188 | wrmsr(MSR_POWER_CTL, msr); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 189 | |
Patrick Rudolph | ea04a53 | 2023-10-20 14:17:24 +0200 | [diff] [blame] | 190 | /* C3 Interrupt Response Time Limit */ |
| 191 | msr.hi = 0; |
| 192 | msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50; |
| 193 | wrmsr(MSR_PKGC3_IRTL, msr); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 194 | |
Patrick Rudolph | ea04a53 | 2023-10-20 14:17:24 +0200 | [diff] [blame] | 195 | /* C6 Interrupt Response Time Limit */ |
| 196 | msr.hi = 0; |
| 197 | msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68; |
| 198 | wrmsr(MSR_PKGC6_IRTL, msr); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 199 | |
Patrick Rudolph | ea04a53 | 2023-10-20 14:17:24 +0200 | [diff] [blame] | 200 | /* C7 Interrupt Response Time Limit */ |
| 201 | msr.hi = 0; |
| 202 | msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D; |
| 203 | wrmsr(MSR_PKGC7_IRTL, msr); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 204 | |
Patrick Rudolph | ea04a53 | 2023-10-20 14:17:24 +0200 | [diff] [blame] | 205 | /* Primary Plane Current Limit */ |
| 206 | msr = rdmsr(MSR_PP0_CURRENT_CONFIG); |
| 207 | msr.lo &= ~0x1fff; |
| 208 | msr.lo |= PP0_CURRENT_LIMIT; |
Patrick Rudolph | 8685205 | 2023-10-20 14:37:07 +0200 | [diff] [blame^] | 209 | msr.lo |= PP0_CURRENT_LIMIT_LOCK; |
Patrick Rudolph | ea04a53 | 2023-10-20 14:17:24 +0200 | [diff] [blame] | 210 | wrmsr(MSR_PP0_CURRENT_CONFIG, msr); |
| 211 | |
| 212 | /* Secondary Plane Current Limit */ |
| 213 | msr = rdmsr(MSR_PP1_CURRENT_CONFIG); |
| 214 | msr.lo &= ~0x1fff; |
| 215 | if (cpuid_eax(1) >= 0x30600) |
| 216 | msr.lo |= PP1_CURRENT_LIMIT_IVB; |
| 217 | else |
| 218 | msr.lo |= PP1_CURRENT_LIMIT_SNB; |
Patrick Rudolph | 8685205 | 2023-10-20 14:37:07 +0200 | [diff] [blame^] | 219 | msr.lo |= PP1_CURRENT_LIMIT_LOCK; |
Patrick Rudolph | ea04a53 | 2023-10-20 14:17:24 +0200 | [diff] [blame] | 220 | wrmsr(MSR_PP1_CURRENT_CONFIG, msr); |
| 221 | } |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 222 | } |
| 223 | |
Arthur Heymans | cdb26fd | 2021-11-15 20:12:02 +0100 | [diff] [blame] | 224 | static void configure_thermal_target(struct device *dev) |
Duncan Laurie | 5563211 | 2012-07-16 12:19:00 -0700 | [diff] [blame] | 225 | { |
Arthur Heymans | cdb26fd | 2021-11-15 20:12:02 +0100 | [diff] [blame] | 226 | struct cpu_intel_model_206ax_config *conf = dev->bus->dev->chip_info; |
Duncan Laurie | 5563211 | 2012-07-16 12:19:00 -0700 | [diff] [blame] | 227 | msr_t msr; |
| 228 | |
Patrick Rudolph | ea04a53 | 2023-10-20 14:17:24 +0200 | [diff] [blame] | 229 | if (boot_cpu()) { |
| 230 | /* |
| 231 | * The following MSR is in scope 'Package', thus it's sufficient |
| 232 | * to write it once on one core. |
| 233 | */ |
| 234 | |
| 235 | /* Set TCC activation offset if supported */ |
| 236 | msr = rdmsr(MSR_PLATFORM_INFO); |
| 237 | if ((msr.lo & (1 << 30)) && conf->tcc_offset) { |
| 238 | msr = rdmsr(MSR_TEMPERATURE_TARGET); |
| 239 | msr.lo &= ~(0xf << 24); /* Bits 27:24 */ |
| 240 | msr.lo |= (conf->tcc_offset & 0xf) << 24; |
| 241 | wrmsr(MSR_TEMPERATURE_TARGET, msr); |
| 242 | } |
Duncan Laurie | 5563211 | 2012-07-16 12:19:00 -0700 | [diff] [blame] | 243 | } |
| 244 | } |
| 245 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 246 | static void configure_misc(void) |
| 247 | { |
| 248 | msr_t msr; |
| 249 | |
| 250 | msr = rdmsr(IA32_MISC_ENABLE); |
| 251 | msr.lo |= (1 << 0); /* Fast String enable */ |
Lee Leahy | 7b5f12b9 | 2017-03-15 17:16:59 -0700 | [diff] [blame] | 252 | msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 253 | msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ |
| 254 | wrmsr(IA32_MISC_ENABLE, msr); |
| 255 | |
| 256 | /* Disable Thermal interrupts */ |
| 257 | msr.lo = 0; |
| 258 | msr.hi = 0; |
| 259 | wrmsr(IA32_THERM_INTERRUPT, msr); |
| 260 | |
Patrick Rudolph | ea04a53 | 2023-10-20 14:17:24 +0200 | [diff] [blame] | 261 | if (boot_cpu()) { |
| 262 | /* |
| 263 | * The following MSR is in scope 'Package', thus it's sufficient |
| 264 | * to write it once on one core. |
| 265 | */ |
| 266 | |
| 267 | /* Enable package critical interrupt only */ |
| 268 | msr.lo = 1 << 4; |
| 269 | msr.hi = 0; |
| 270 | wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); |
| 271 | } |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 272 | } |
| 273 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 274 | static void set_max_ratio(void) |
| 275 | { |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 276 | msr_t msr, perf_ctl; |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 277 | |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 278 | perf_ctl.hi = 0; |
| 279 | |
| 280 | /* Check for configurable TDP option */ |
| 281 | if (cpu_config_tdp_levels()) { |
| 282 | /* Set to nominal TDP ratio */ |
| 283 | msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); |
| 284 | perf_ctl.lo = (msr.lo & 0xff) << 8; |
| 285 | } else { |
| 286 | /* Platform Info bits 15:8 give max ratio */ |
| 287 | msr = rdmsr(MSR_PLATFORM_INFO); |
| 288 | perf_ctl.lo = msr.lo & 0xff00; |
| 289 | } |
| 290 | wrmsr(IA32_PERF_CTL, perf_ctl); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 291 | |
| 292 | printk(BIOS_DEBUG, "model_x06ax: frequency set to %d\n", |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 293 | ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 294 | } |
| 295 | |
Michał Żygowski | 0d11dbf | 2020-10-31 21:43:25 +0100 | [diff] [blame] | 296 | unsigned int smbios_cpu_get_max_speed_mhz(void) |
| 297 | { |
| 298 | msr_t msr; |
| 299 | msr = rdmsr(MSR_TURBO_RATIO_LIMIT); |
| 300 | return (msr.lo & 0xff) * SANDYBRIDGE_BCLK; |
| 301 | } |
| 302 | |
| 303 | unsigned int smbios_cpu_get_current_speed_mhz(void) |
| 304 | { |
| 305 | msr_t msr; |
| 306 | msr = rdmsr(MSR_PLATFORM_INFO); |
| 307 | return ((msr.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK; |
| 308 | } |
| 309 | |
| 310 | unsigned int smbios_processor_external_clock(void) |
| 311 | { |
| 312 | return SANDYBRIDGE_BCLK; |
| 313 | } |
| 314 | |
Patrick Rudolph | 9e1b9b5 | 2018-07-27 17:25:05 +0200 | [diff] [blame] | 315 | static void model_206ax_report(void) |
| 316 | { |
| 317 | static const char *const mode[] = {"NOT ", ""}; |
Patrick Rudolph | 9e1b9b5 | 2018-07-27 17:25:05 +0200 | [diff] [blame] | 318 | char processor_name[49]; |
| 319 | int vt, txt, aes; |
Subrata Banik | 53b08c3 | 2018-12-10 14:11:35 +0530 | [diff] [blame] | 320 | uint32_t cpu_id, cpu_feature_flag; |
Patrick Rudolph | 9e1b9b5 | 2018-07-27 17:25:05 +0200 | [diff] [blame] | 321 | |
| 322 | /* Print processor name */ |
| 323 | fill_processor_name(processor_name); |
| 324 | printk(BIOS_INFO, "CPU: %s.\n", processor_name); |
| 325 | |
| 326 | /* Print platform ID */ |
| 327 | printk(BIOS_INFO, "CPU: platform id %x\n", get_platform_id()); |
| 328 | |
| 329 | /* CPUID and features */ |
Subrata Banik | 53b08c3 | 2018-12-10 14:11:35 +0530 | [diff] [blame] | 330 | cpu_id = cpu_get_cpuid(); |
| 331 | printk(BIOS_INFO, "CPU: cpuid(1) 0x%x\n", cpu_id); |
| 332 | |
| 333 | cpu_feature_flag = cpu_get_feature_flags_ecx(); |
| 334 | aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0; |
| 335 | txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0; |
| 336 | vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0; |
Patrick Rudolph | 9e1b9b5 | 2018-07-27 17:25:05 +0200 | [diff] [blame] | 337 | printk(BIOS_INFO, "CPU: AES %ssupported\n", mode[aes]); |
| 338 | printk(BIOS_INFO, "CPU: TXT %ssupported\n", mode[txt]); |
| 339 | printk(BIOS_INFO, "CPU: VT %ssupported\n", mode[vt]); |
| 340 | } |
| 341 | |
Edward O'Callaghan | 2c9d2cf | 2014-10-27 23:29:29 +1100 | [diff] [blame] | 342 | static void model_206ax_init(struct device *cpu) |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 343 | { |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 344 | /* Clear out pending MCEs */ |
Felix Held | acbf154 | 2021-07-13 16:44:18 +0200 | [diff] [blame] | 345 | /* This should only be done on a cold boot */ |
| 346 | mca_clear_status(); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 347 | |
Patrick Rudolph | 9e1b9b5 | 2018-07-27 17:25:05 +0200 | [diff] [blame] | 348 | /* Print infos */ |
| 349 | model_206ax_report(); |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 350 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 351 | /* Setup Page Attribute Tables (PAT) */ |
| 352 | // TODO set up PAT |
| 353 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 354 | enable_lapic_tpr(); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 355 | |
Matt DeVillier | ed6fe2f | 2016-12-14 16:12:43 -0600 | [diff] [blame] | 356 | /* Set virtualization based on Kconfig option */ |
Matt DeVillier | f9aed65 | 2018-12-15 15:57:33 -0600 | [diff] [blame] | 357 | set_vmx_and_lock(); |
Marc Jones | 5986eda | 2012-10-25 09:37:19 -0600 | [diff] [blame] | 358 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 359 | /* Configure C States */ |
| 360 | configure_c_states(); |
| 361 | |
| 362 | /* Configure Enhanced SpeedStep and Thermal Sensors */ |
| 363 | configure_misc(); |
| 364 | |
Duncan Laurie | 5563211 | 2012-07-16 12:19:00 -0700 | [diff] [blame] | 365 | /* Thermal throttle activation offset */ |
Arthur Heymans | cdb26fd | 2021-11-15 20:12:02 +0100 | [diff] [blame] | 366 | configure_thermal_target(cpu); |
Duncan Laurie | 5563211 | 2012-07-16 12:19:00 -0700 | [diff] [blame] | 367 | |
Michael Niewöhner | 6303243 | 2020-10-11 17:34:54 +0200 | [diff] [blame] | 368 | set_aesni_lock(); |
Michael Niewöhner | 7f8767d | 2020-10-18 00:45:38 +0200 | [diff] [blame] | 369 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 370 | /* Enable Direct Cache Access */ |
| 371 | configure_dca_cap(); |
| 372 | |
| 373 | /* Set energy policy */ |
| 374 | set_energy_perf_bias(ENERGY_POLICY_NORMAL); |
| 375 | |
| 376 | /* Set Max Ratio */ |
| 377 | set_max_ratio(); |
| 378 | |
| 379 | /* Enable Turbo */ |
| 380 | enable_turbo(); |
Arthur Heymans | edbf5d9 | 2018-01-25 20:03:42 +0100 | [diff] [blame] | 381 | } |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 382 | |
Arthur Heymans | edbf5d9 | 2018-01-25 20:03:42 +0100 | [diff] [blame] | 383 | /* MP initialization support. */ |
Arthur Heymans | edbf5d9 | 2018-01-25 20:03:42 +0100 | [diff] [blame] | 384 | static void pre_mp_init(void) |
| 385 | { |
| 386 | /* Setup MTRRs based on physical address size. */ |
| 387 | x86_setup_mtrrs_with_detect(); |
| 388 | x86_mtrr_check(); |
| 389 | } |
| 390 | |
| 391 | static int get_cpu_count(void) |
| 392 | { |
| 393 | msr_t msr; |
Angel Pons | 04c497a | 2021-11-03 16:30:10 +0100 | [diff] [blame] | 394 | unsigned int num_threads; |
| 395 | unsigned int num_cores; |
Arthur Heymans | edbf5d9 | 2018-01-25 20:03:42 +0100 | [diff] [blame] | 396 | |
Elyes HAOUAS | a6a396d | 2019-05-26 13:25:30 +0200 | [diff] [blame] | 397 | msr = rdmsr(MSR_CORE_THREAD_COUNT); |
Arthur Heymans | edbf5d9 | 2018-01-25 20:03:42 +0100 | [diff] [blame] | 398 | num_threads = (msr.lo >> 0) & 0xffff; |
| 399 | num_cores = (msr.lo >> 16) & 0xffff; |
| 400 | printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n", |
| 401 | num_cores, num_threads); |
| 402 | |
| 403 | return num_threads; |
| 404 | } |
| 405 | |
| 406 | static void get_microcode_info(const void **microcode, int *parallel) |
| 407 | { |
Patrick Rudolph | 3fa23b8 | 2021-01-25 09:42:08 +0100 | [diff] [blame] | 408 | *microcode = intel_microcode_find(); |
Patrick Rudolph | ce51b34 | 2021-01-11 09:21:58 +0100 | [diff] [blame] | 409 | *parallel = !intel_ht_supported(); |
Arthur Heymans | edbf5d9 | 2018-01-25 20:03:42 +0100 | [diff] [blame] | 410 | } |
| 411 | |
| 412 | static void per_cpu_smm_trigger(void) |
| 413 | { |
| 414 | /* Relocate the SMM handler. */ |
| 415 | smm_relocate(); |
| 416 | |
| 417 | /* After SMM relocation a 2nd microcode load is required. */ |
Patrick Rudolph | 3fa23b8 | 2021-01-25 09:42:08 +0100 | [diff] [blame] | 418 | const void *microcode_patch = intel_microcode_find(); |
Arthur Heymans | edbf5d9 | 2018-01-25 20:03:42 +0100 | [diff] [blame] | 419 | intel_microcode_load_unlocked(microcode_patch); |
| 420 | } |
| 421 | |
| 422 | static void post_mp_init(void) |
| 423 | { |
| 424 | /* Now that all APs have been relocated as well as the BSP let SMIs |
| 425 | * start flowing. */ |
Kyösti Mälkki | 0778c86 | 2020-06-10 12:44:03 +0300 | [diff] [blame] | 426 | global_smi_enable(); |
Arthur Heymans | edbf5d9 | 2018-01-25 20:03:42 +0100 | [diff] [blame] | 427 | |
| 428 | /* Lock down the SMRAM space. */ |
| 429 | smm_lock(); |
| 430 | } |
| 431 | |
Arthur Heymans | edbf5d9 | 2018-01-25 20:03:42 +0100 | [diff] [blame] | 432 | static const struct mp_ops mp_ops = { |
| 433 | .pre_mp_init = pre_mp_init, |
| 434 | .get_cpu_count = get_cpu_count, |
| 435 | .get_smm_info = smm_info, |
| 436 | .get_microcode_info = get_microcode_info, |
| 437 | .pre_mp_smm_init = smm_initialize, |
| 438 | .per_cpu_smm_trigger = per_cpu_smm_trigger, |
| 439 | .relocation_handler = smm_relocation_handler, |
| 440 | .post_mp_init = post_mp_init, |
| 441 | }; |
| 442 | |
Kyösti Mälkki | b3267e0 | 2019-08-13 16:44:04 +0300 | [diff] [blame] | 443 | void mp_init_cpus(struct bus *cpu_bus) |
Arthur Heymans | edbf5d9 | 2018-01-25 20:03:42 +0100 | [diff] [blame] | 444 | { |
Felix Held | 4dd7d11 | 2021-10-20 23:31:43 +0200 | [diff] [blame] | 445 | /* TODO: Handle mp_init_with_smm failure? */ |
| 446 | mp_init_with_smm(cpu_bus, &mp_ops); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 447 | } |
| 448 | |
| 449 | static struct device_operations cpu_dev_ops = { |
| 450 | .init = model_206ax_init, |
| 451 | }; |
| 452 | |
Jonathan Neuschäfer | 8f06ce3 | 2017-11-20 01:56:44 +0100 | [diff] [blame] | 453 | static const struct cpu_device_id cpu_table[] = { |
Felix Held | a5aee11 | 2023-02-06 17:01:59 +0100 | [diff] [blame] | 454 | { X86_VENDOR_INTEL, 0x206a0, CPUID_ALL_STEPPINGS_MASK }, /* Intel Sandybridge */ |
| 455 | { X86_VENDOR_INTEL, 0x306a0, CPUID_ALL_STEPPINGS_MASK }, /* Intel IvyBridge */ |
Felix Held | 1e78165 | 2023-02-08 11:39:16 +0100 | [diff] [blame] | 456 | CPU_TABLE_END |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 457 | }; |
| 458 | |
| 459 | static const struct cpu_driver driver __cpu_driver = { |
| 460 | .ops = &cpu_dev_ops, |
| 461 | .id_table = cpu_table, |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 462 | }; |