Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
| 20 | * MA 02110-1301 USA |
| 21 | */ |
| 22 | |
| 23 | #include <console/console.h> |
| 24 | #include <device/device.h> |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 25 | #include <string.h> |
| 26 | #include <arch/acpi.h> |
| 27 | #include <cpu/cpu.h> |
| 28 | #include <cpu/x86/mtrr.h> |
| 29 | #include <cpu/x86/msr.h> |
| 30 | #include <cpu/x86/lapic.h> |
| 31 | #include <cpu/intel/microcode.h> |
| 32 | #include <cpu/intel/speedstep.h> |
| 33 | #include <cpu/intel/turbo.h> |
| 34 | #include <cpu/x86/cache.h> |
| 35 | #include <cpu/x86/name.h> |
| 36 | #include <pc80/mc146818rtc.h> |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 37 | #include "model_206ax.h" |
Duncan Laurie | 5563211 | 2012-07-16 12:19:00 -0700 | [diff] [blame] | 38 | #include "chip.h" |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 39 | |
| 40 | /* |
Martin Roth | 4c3ab73 | 2013-07-08 16:23:54 -0600 | [diff] [blame] | 41 | * List of supported C-states in this processor |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 42 | * |
| 43 | * Latencies are typical worst-case package exit time in uS |
| 44 | * taken from the SandyBridge BIOS specification. |
| 45 | */ |
| 46 | static acpi_cstate_t cstate_map[] = { |
| 47 | { /* 0: C0 */ |
| 48 | },{ /* 1: C1 */ |
| 49 | .latency = 1, |
| 50 | .power = 1000, |
| 51 | .resource = { |
| 52 | .addrl = 0x00, /* MWAIT State 0 */ |
| 53 | .space_id = ACPI_ADDRESS_SPACE_FIXED, |
| 54 | .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, |
| 55 | .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, |
| 56 | .resv = ACPI_FFIXEDHW_FLAG_HW_COORD, |
| 57 | } |
| 58 | }, |
| 59 | { /* 2: C1E */ |
| 60 | .latency = 1, |
| 61 | .power = 1000, |
| 62 | .resource = { |
| 63 | .addrl = 0x01, /* MWAIT State 0 Sub-state 1 */ |
| 64 | .space_id = ACPI_ADDRESS_SPACE_FIXED, |
| 65 | .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, |
| 66 | .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, |
| 67 | .resv = ACPI_FFIXEDHW_FLAG_HW_COORD, |
| 68 | } |
| 69 | }, |
| 70 | { /* 3: C3 */ |
| 71 | .latency = 63, |
| 72 | .power = 500, |
| 73 | .resource = { |
| 74 | .addrl = 0x10, /* MWAIT State 1 */ |
| 75 | .space_id = ACPI_ADDRESS_SPACE_FIXED, |
| 76 | .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, |
| 77 | .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, |
| 78 | .resv = ACPI_FFIXEDHW_FLAG_HW_COORD, |
| 79 | } |
| 80 | }, |
| 81 | { /* 4: C6 */ |
| 82 | .latency = 87, |
| 83 | .power = 350, |
| 84 | .resource = { |
| 85 | .addrl = 0x20, /* MWAIT State 2 */ |
| 86 | .space_id = ACPI_ADDRESS_SPACE_FIXED, |
| 87 | .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, |
| 88 | .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, |
| 89 | .resv = ACPI_FFIXEDHW_FLAG_HW_COORD, |
| 90 | } |
| 91 | }, |
| 92 | { /* 5: C7 */ |
| 93 | .latency = 90, |
| 94 | .power = 200, |
| 95 | .resource = { |
| 96 | .addrl = 0x30, /* MWAIT State 3 */ |
| 97 | .space_id = ACPI_ADDRESS_SPACE_FIXED, |
| 98 | .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, |
| 99 | .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, |
| 100 | .resv = ACPI_FFIXEDHW_FLAG_HW_COORD, |
| 101 | } |
| 102 | }, |
| 103 | { /* 6: C7S */ |
| 104 | .latency = 90, |
| 105 | .power = 200, |
| 106 | .resource = { |
| 107 | .addrl = 0x31, /* MWAIT State 3 Sub-state 1 */ |
| 108 | .space_id = ACPI_ADDRESS_SPACE_FIXED, |
| 109 | .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, |
| 110 | .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, |
| 111 | .resv = ACPI_FFIXEDHW_FLAG_HW_COORD, |
| 112 | } |
| 113 | }, |
| 114 | { 0 } |
| 115 | }; |
| 116 | |
Marc Jones | 5986eda | 2012-10-25 09:37:19 -0600 | [diff] [blame] | 117 | static void enable_vmx(void) |
| 118 | { |
| 119 | struct cpuid_result regs; |
| 120 | msr_t msr; |
| 121 | int enable = CONFIG_ENABLE_VMX; |
| 122 | |
Marc Jones | f5a11aa | 2012-10-25 14:01:37 -0600 | [diff] [blame] | 123 | regs = cpuid(1); |
| 124 | /* Check that the VMX is supported before reading or writing the MSR. */ |
| 125 | if (!((regs.ecx & CPUID_VMX) || (regs.ecx & CPUID_SMX))) |
| 126 | return; |
| 127 | |
Marc Jones | 5986eda | 2012-10-25 09:37:19 -0600 | [diff] [blame] | 128 | msr = rdmsr(IA32_FEATURE_CONTROL); |
| 129 | |
| 130 | if (msr.lo & (1 << 0)) { |
Marc Jones | f5a11aa | 2012-10-25 14:01:37 -0600 | [diff] [blame] | 131 | printk(BIOS_ERR, "VMX is locked, so %s will do nothing\n", __func__); |
Marc Jones | 5986eda | 2012-10-25 09:37:19 -0600 | [diff] [blame] | 132 | /* VMX locked. If we set it again we get an illegal |
| 133 | * instruction |
| 134 | */ |
| 135 | return; |
| 136 | } |
| 137 | |
Marc Jones | f5a11aa | 2012-10-25 14:01:37 -0600 | [diff] [blame] | 138 | /* The IA32_FEATURE_CONTROL MSR may initialize with random values. |
| 139 | * It must be cleared regardless of VMX config setting. |
| 140 | */ |
| 141 | msr.hi = msr.lo = 0; |
Marc Jones | 5986eda | 2012-10-25 09:37:19 -0600 | [diff] [blame] | 142 | |
Marc Jones | f5a11aa | 2012-10-25 14:01:37 -0600 | [diff] [blame] | 143 | printk(BIOS_DEBUG, "%s VMX\n", enable ? "Enabling" : "Disabling"); |
| 144 | |
Mike Frysinger | 223af0d | 2013-02-08 17:45:27 -0500 | [diff] [blame] | 145 | /* Even though the Intel manual says you must set the lock bit in addition |
| 146 | * to the VMX bit in order for VMX to work, it is incorrect. Thus we leave |
| 147 | * it unlocked for the OS to manage things itself. This is good for a few |
| 148 | * reasons: |
| 149 | * - No need to reflash the bios just to toggle the lock bit. |
| 150 | * - The VMX bits really really should match each other across cores, so |
| 151 | * hard locking it on one while another has the opposite setting can |
| 152 | * easily lead to crashes as code using VMX migrates between them. |
| 153 | * - Vendors that want to "upsell" from a bios that disables+locks to |
| 154 | * one that doesn't is sleazy. |
| 155 | * By leaving this to the OS (e.g. Linux), people can do exactly what they |
| 156 | * want on the fly, and do it correctly (e.g. across multiple cores). |
| 157 | */ |
Marc Jones | f5a11aa | 2012-10-25 14:01:37 -0600 | [diff] [blame] | 158 | if (enable) { |
Mike Frysinger | 223af0d | 2013-02-08 17:45:27 -0500 | [diff] [blame] | 159 | msr.lo |= (1 << 2); |
| 160 | if (regs.ecx & CPUID_SMX) |
| 161 | msr.lo |= (1 << 1); |
Marc Jones | 5986eda | 2012-10-25 09:37:19 -0600 | [diff] [blame] | 162 | } |
| 163 | |
| 164 | wrmsr(IA32_FEATURE_CONTROL, msr); |
| 165 | } |
| 166 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 167 | /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ |
| 168 | static const u8 power_limit_time_sec_to_msr[] = { |
| 169 | [0] = 0x00, |
| 170 | [1] = 0x0a, |
| 171 | [2] = 0x0b, |
| 172 | [3] = 0x4b, |
| 173 | [4] = 0x0c, |
| 174 | [5] = 0x2c, |
| 175 | [6] = 0x4c, |
| 176 | [7] = 0x6c, |
| 177 | [8] = 0x0d, |
| 178 | [10] = 0x2d, |
| 179 | [12] = 0x4d, |
| 180 | [14] = 0x6d, |
| 181 | [16] = 0x0e, |
| 182 | [20] = 0x2e, |
| 183 | [24] = 0x4e, |
| 184 | [28] = 0x6e, |
| 185 | [32] = 0x0f, |
| 186 | [40] = 0x2f, |
| 187 | [48] = 0x4f, |
| 188 | [56] = 0x6f, |
| 189 | [64] = 0x10, |
| 190 | [80] = 0x30, |
| 191 | [96] = 0x50, |
| 192 | [112] = 0x70, |
| 193 | [128] = 0x11, |
| 194 | }; |
| 195 | |
| 196 | /* Convert POWER_LIMIT_1_TIME MSR value to seconds */ |
| 197 | static const u8 power_limit_time_msr_to_sec[] = { |
| 198 | [0x00] = 0, |
| 199 | [0x0a] = 1, |
| 200 | [0x0b] = 2, |
| 201 | [0x4b] = 3, |
| 202 | [0x0c] = 4, |
| 203 | [0x2c] = 5, |
| 204 | [0x4c] = 6, |
| 205 | [0x6c] = 7, |
| 206 | [0x0d] = 8, |
| 207 | [0x2d] = 10, |
| 208 | [0x4d] = 12, |
| 209 | [0x6d] = 14, |
| 210 | [0x0e] = 16, |
| 211 | [0x2e] = 20, |
| 212 | [0x4e] = 24, |
| 213 | [0x6e] = 28, |
| 214 | [0x0f] = 32, |
| 215 | [0x2f] = 40, |
| 216 | [0x4f] = 48, |
| 217 | [0x6f] = 56, |
| 218 | [0x10] = 64, |
| 219 | [0x30] = 80, |
| 220 | [0x50] = 96, |
| 221 | [0x70] = 112, |
| 222 | [0x11] = 128, |
| 223 | }; |
| 224 | |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 225 | int cpu_config_tdp_levels(void) |
| 226 | { |
| 227 | msr_t platform_info; |
| 228 | |
| 229 | /* Minimum CPU revision */ |
| 230 | if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID) |
| 231 | return 0; |
| 232 | |
| 233 | /* Bits 34:33 indicate how many levels supported */ |
| 234 | platform_info = rdmsr(MSR_PLATFORM_INFO); |
| 235 | return (platform_info.hi >> 1) & 3; |
| 236 | } |
| 237 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 238 | /* |
| 239 | * Configure processor power limits if possible |
| 240 | * This must be done AFTER set of BIOS_RESET_CPL |
| 241 | */ |
| 242 | void set_power_limits(u8 power_limit_1_time) |
| 243 | { |
| 244 | msr_t msr = rdmsr(MSR_PLATFORM_INFO); |
| 245 | msr_t limit; |
| 246 | unsigned power_unit; |
| 247 | unsigned tdp, min_power, max_power, max_time; |
| 248 | u8 power_limit_1_val; |
| 249 | |
Edward O'Callaghan | 5cfef13 | 2014-08-03 20:00:47 +1000 | [diff] [blame^] | 250 | if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 251 | return; |
| 252 | |
| 253 | if (!(msr.lo & PLATFORM_INFO_SET_TDP)) |
| 254 | return; |
| 255 | |
| 256 | /* Get units */ |
| 257 | msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); |
| 258 | power_unit = 2 << ((msr.lo & 0xf) - 1); |
| 259 | |
| 260 | /* Get power defaults for this SKU */ |
| 261 | msr = rdmsr(MSR_PKG_POWER_SKU); |
| 262 | tdp = msr.lo & 0x7fff; |
| 263 | min_power = (msr.lo >> 16) & 0x7fff; |
| 264 | max_power = msr.hi & 0x7fff; |
| 265 | max_time = (msr.hi >> 16) & 0x7f; |
| 266 | |
| 267 | printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit); |
| 268 | |
| 269 | if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time) |
| 270 | power_limit_1_time = power_limit_time_msr_to_sec[max_time]; |
| 271 | |
| 272 | if (min_power > 0 && tdp < min_power) |
| 273 | tdp = min_power; |
| 274 | |
| 275 | if (max_power > 0 && tdp > max_power) |
| 276 | tdp = max_power; |
| 277 | |
| 278 | power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time]; |
| 279 | |
| 280 | /* Set long term power limit to TDP */ |
| 281 | limit.lo = 0; |
| 282 | limit.lo |= tdp & PKG_POWER_LIMIT_MASK; |
| 283 | limit.lo |= PKG_POWER_LIMIT_EN; |
| 284 | limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << |
| 285 | PKG_POWER_LIMIT_TIME_SHIFT; |
| 286 | |
| 287 | /* Set short term power limit to 1.25 * TDP */ |
| 288 | limit.hi = 0; |
| 289 | limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK; |
| 290 | limit.hi |= PKG_POWER_LIMIT_EN; |
| 291 | /* Power limit 2 time is only programmable on SNB EP/EX */ |
| 292 | |
| 293 | wrmsr(MSR_PKG_POWER_LIMIT, limit); |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 294 | |
| 295 | /* Use nominal TDP values for CPUs with configurable TDP */ |
| 296 | if (cpu_config_tdp_levels()) { |
| 297 | msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); |
| 298 | limit.hi = 0; |
| 299 | limit.lo = msr.lo & 0xff; |
| 300 | wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit); |
| 301 | } |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 302 | } |
| 303 | |
| 304 | static void configure_c_states(void) |
| 305 | { |
| 306 | msr_t msr; |
| 307 | |
| 308 | msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); |
| 309 | msr.lo |= (1 << 28); // C1 Auto Undemotion Enable |
| 310 | msr.lo |= (1 << 27); // C3 Auto Undemotion Enable |
| 311 | msr.lo |= (1 << 26); // C1 Auto Demotion Enable |
| 312 | msr.lo |= (1 << 25); // C3 Auto Demotion Enable |
| 313 | msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection |
| 314 | msr.lo |= 7; // No package C-state limit |
| 315 | wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); |
| 316 | |
Patrick Georgi | 644e83b | 2013-02-09 15:35:30 +0100 | [diff] [blame] | 317 | msr = rdmsr(MSR_PMG_IO_CAPTURE_ADDR); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 318 | msr.lo &= ~0x7ffff; |
| 319 | msr.lo |= (PMB0_BASE + 4); // LVL_2 base address |
| 320 | msr.lo |= (2 << 16); // CST Range: C7 is max C-state |
Patrick Georgi | 644e83b | 2013-02-09 15:35:30 +0100 | [diff] [blame] | 321 | wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 322 | |
| 323 | msr = rdmsr(MSR_MISC_PWR_MGMT); |
| 324 | msr.lo &= ~(1 << 0); // Enable P-state HW_ALL coordination |
| 325 | wrmsr(MSR_MISC_PWR_MGMT, msr); |
| 326 | |
| 327 | msr = rdmsr(MSR_POWER_CTL); |
| 328 | msr.lo |= (1 << 18); // Enable Energy Perf Bias MSR 0x1b0 |
| 329 | msr.lo |= (1 << 1); // C1E Enable |
| 330 | msr.lo |= (1 << 0); // Bi-directional PROCHOT# |
| 331 | wrmsr(MSR_POWER_CTL, msr); |
| 332 | |
| 333 | /* C3 Interrupt Response Time Limit */ |
| 334 | msr.hi = 0; |
| 335 | msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50; |
| 336 | wrmsr(MSR_PKGC3_IRTL, msr); |
| 337 | |
| 338 | /* C6 Interrupt Response Time Limit */ |
| 339 | msr.hi = 0; |
| 340 | msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68; |
| 341 | wrmsr(MSR_PKGC6_IRTL, msr); |
| 342 | |
| 343 | /* C7 Interrupt Response Time Limit */ |
| 344 | msr.hi = 0; |
| 345 | msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D; |
| 346 | wrmsr(MSR_PKGC7_IRTL, msr); |
| 347 | |
| 348 | /* Primary Plane Current Limit */ |
| 349 | msr = rdmsr(MSR_PP0_CURRENT_CONFIG); |
| 350 | msr.lo &= ~0x1fff; |
| 351 | msr.lo |= PP0_CURRENT_LIMIT; |
| 352 | wrmsr(MSR_PP0_CURRENT_CONFIG, msr); |
| 353 | |
| 354 | /* Secondary Plane Current Limit */ |
| 355 | msr = rdmsr(MSR_PP1_CURRENT_CONFIG); |
| 356 | msr.lo &= ~0x1fff; |
Duncan Laurie | 4e4320f | 2012-06-25 09:53:58 -0700 | [diff] [blame] | 357 | if (cpuid_eax(1) >= 0x30600) |
| 358 | msr.lo |= PP1_CURRENT_LIMIT_IVB; |
| 359 | else |
| 360 | msr.lo |= PP1_CURRENT_LIMIT_SNB; |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 361 | wrmsr(MSR_PP1_CURRENT_CONFIG, msr); |
| 362 | } |
| 363 | |
Duncan Laurie | 5563211 | 2012-07-16 12:19:00 -0700 | [diff] [blame] | 364 | static void configure_thermal_target(void) |
| 365 | { |
| 366 | struct cpu_intel_model_206ax_config *conf; |
| 367 | device_t lapic; |
| 368 | msr_t msr; |
| 369 | |
| 370 | /* Find pointer to CPU configuration */ |
| 371 | lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); |
| 372 | if (!lapic || !lapic->chip_info) |
| 373 | return; |
| 374 | conf = lapic->chip_info; |
| 375 | |
Martin Roth | 4c3ab73 | 2013-07-08 16:23:54 -0600 | [diff] [blame] | 376 | /* Set TCC activation offset if supported */ |
Duncan Laurie | 5563211 | 2012-07-16 12:19:00 -0700 | [diff] [blame] | 377 | msr = rdmsr(MSR_PLATFORM_INFO); |
| 378 | if ((msr.lo & (1 << 30)) && conf->tcc_offset) { |
| 379 | msr = rdmsr(MSR_TEMPERATURE_TARGET); |
| 380 | msr.lo &= ~(0xf << 24); /* Bits 27:24 */ |
| 381 | msr.lo |= (conf->tcc_offset & 0xf) << 24; |
| 382 | wrmsr(MSR_TEMPERATURE_TARGET, msr); |
| 383 | } |
| 384 | } |
| 385 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 386 | static void configure_misc(void) |
| 387 | { |
| 388 | msr_t msr; |
| 389 | |
| 390 | msr = rdmsr(IA32_MISC_ENABLE); |
| 391 | msr.lo |= (1 << 0); /* Fast String enable */ |
| 392 | msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ |
| 393 | msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ |
| 394 | wrmsr(IA32_MISC_ENABLE, msr); |
| 395 | |
| 396 | /* Disable Thermal interrupts */ |
| 397 | msr.lo = 0; |
| 398 | msr.hi = 0; |
| 399 | wrmsr(IA32_THERM_INTERRUPT, msr); |
| 400 | |
| 401 | /* Enable package critical interrupt only */ |
| 402 | msr.lo = 1 << 4; |
| 403 | msr.hi = 0; |
| 404 | wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); |
| 405 | } |
| 406 | |
| 407 | static void enable_lapic_tpr(void) |
| 408 | { |
| 409 | msr_t msr; |
| 410 | |
| 411 | msr = rdmsr(MSR_PIC_MSG_CONTROL); |
| 412 | msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ |
| 413 | wrmsr(MSR_PIC_MSG_CONTROL, msr); |
| 414 | } |
| 415 | |
| 416 | static void configure_dca_cap(void) |
| 417 | { |
| 418 | struct cpuid_result cpuid_regs; |
| 419 | msr_t msr; |
| 420 | |
| 421 | /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ |
| 422 | cpuid_regs = cpuid(1); |
| 423 | if (cpuid_regs.ecx & (1 << 18)) { |
| 424 | msr = rdmsr(IA32_PLATFORM_DCA_CAP); |
| 425 | msr.lo |= 1; |
| 426 | wrmsr(IA32_PLATFORM_DCA_CAP, msr); |
| 427 | } |
| 428 | } |
| 429 | |
| 430 | static void set_max_ratio(void) |
| 431 | { |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 432 | msr_t msr, perf_ctl; |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 433 | |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 434 | perf_ctl.hi = 0; |
| 435 | |
| 436 | /* Check for configurable TDP option */ |
| 437 | if (cpu_config_tdp_levels()) { |
| 438 | /* Set to nominal TDP ratio */ |
| 439 | msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); |
| 440 | perf_ctl.lo = (msr.lo & 0xff) << 8; |
| 441 | } else { |
| 442 | /* Platform Info bits 15:8 give max ratio */ |
| 443 | msr = rdmsr(MSR_PLATFORM_INFO); |
| 444 | perf_ctl.lo = msr.lo & 0xff00; |
| 445 | } |
| 446 | wrmsr(IA32_PERF_CTL, perf_ctl); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 447 | |
| 448 | printk(BIOS_DEBUG, "model_x06ax: frequency set to %d\n", |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 449 | ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 450 | } |
| 451 | |
| 452 | static void set_energy_perf_bias(u8 policy) |
| 453 | { |
| 454 | msr_t msr; |
| 455 | |
| 456 | /* Energy Policy is bits 3:0 */ |
| 457 | msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS); |
| 458 | msr.lo &= ~0xf; |
| 459 | msr.lo |= policy & 0xf; |
| 460 | wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr); |
| 461 | |
| 462 | printk(BIOS_DEBUG, "model_x06ax: energy policy set to %u\n", |
| 463 | policy); |
| 464 | } |
| 465 | |
| 466 | static void configure_mca(void) |
| 467 | { |
| 468 | msr_t msr; |
| 469 | int i; |
| 470 | |
| 471 | msr.lo = msr.hi = 0; |
| 472 | /* This should only be done on a cold boot */ |
| 473 | for (i = 0; i < 7; i++) |
| 474 | wrmsr(IA32_MC0_STATUS + (i * 4), msr); |
| 475 | } |
| 476 | |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 477 | /* |
| 478 | * Initialize any extra cores/threads in this package. |
| 479 | */ |
| 480 | static void intel_cores_init(device_t cpu) |
| 481 | { |
| 482 | struct cpuid_result result; |
Stefan Reinauer | bb9dff5 | 2012-10-15 13:45:11 -0700 | [diff] [blame] | 483 | unsigned threads_per_package, threads_per_core, i; |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 484 | |
Stefan Reinauer | bb9dff5 | 2012-10-15 13:45:11 -0700 | [diff] [blame] | 485 | /* Logical processors (threads) per core */ |
| 486 | result = cpuid_ext(0xb, 0); |
| 487 | threads_per_core = result.ebx & 0xffff; |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 488 | |
Stefan Reinauer | bb9dff5 | 2012-10-15 13:45:11 -0700 | [diff] [blame] | 489 | /* Logical processors (threads) per package */ |
| 490 | result = cpuid_ext(0xb, 1); |
| 491 | threads_per_package = result.ebx & 0xffff; |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 492 | |
| 493 | /* Only initialize extra cores from BSP */ |
| 494 | if (cpu->path.apic.apic_id) |
| 495 | return; |
| 496 | |
Stefan Reinauer | bb9dff5 | 2012-10-15 13:45:11 -0700 | [diff] [blame] | 497 | printk(BIOS_DEBUG, "CPU: %u has %u cores, %u threads per core\n", |
| 498 | cpu->path.apic.apic_id, threads_per_package/threads_per_core, |
| 499 | threads_per_core); |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 500 | |
Stefan Reinauer | bb9dff5 | 2012-10-15 13:45:11 -0700 | [diff] [blame] | 501 | for (i = 1; i < threads_per_package; ++i) { |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 502 | struct device_path cpu_path; |
| 503 | device_t new; |
| 504 | |
| 505 | /* Build the cpu device path */ |
| 506 | cpu_path.type = DEVICE_PATH_APIC; |
| 507 | cpu_path.apic.apic_id = |
| 508 | cpu->path.apic.apic_id + i; |
| 509 | |
| 510 | /* Update APIC ID if no hyperthreading */ |
Stefan Reinauer | bb9dff5 | 2012-10-15 13:45:11 -0700 | [diff] [blame] | 511 | if (threads_per_core == 1) |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 512 | cpu_path.apic.apic_id <<= 1; |
| 513 | |
| 514 | /* Allocate the new cpu device structure */ |
| 515 | new = alloc_dev(cpu->bus, &cpu_path); |
| 516 | if (!new) |
| 517 | continue; |
| 518 | |
| 519 | printk(BIOS_DEBUG, "CPU: %u has core %u\n", |
| 520 | cpu->path.apic.apic_id, |
| 521 | new->path.apic.apic_id); |
| 522 | |
Stefan Reinauer | 455f4b4 | 2012-11-12 15:17:24 -0800 | [diff] [blame] | 523 | #if CONFIG_SMP && CONFIG_MAX_CPUS > 1 |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 524 | /* Start the new cpu */ |
| 525 | if (!start_cpu(new)) { |
| 526 | /* Record the error in cpu? */ |
| 527 | printk(BIOS_ERR, "CPU %u would not start!\n", |
| 528 | new->path.apic.apic_id); |
| 529 | } |
Stefan Reinauer | 455f4b4 | 2012-11-12 15:17:24 -0800 | [diff] [blame] | 530 | #endif |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 531 | } |
| 532 | } |
| 533 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 534 | static void model_206ax_init(device_t cpu) |
| 535 | { |
| 536 | char processor_name[49]; |
| 537 | struct cpuid_result cpuid_regs; |
| 538 | |
| 539 | /* Turn on caching if we haven't already */ |
| 540 | x86_enable_cache(); |
| 541 | |
Vadim Bendebury | 537b4e0 | 2012-06-19 12:56:57 -0700 | [diff] [blame] | 542 | intel_update_microcode_from_cbfs(); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 543 | |
| 544 | /* Clear out pending MCEs */ |
| 545 | configure_mca(); |
| 546 | |
| 547 | /* Print processor name */ |
| 548 | fill_processor_name(processor_name); |
| 549 | printk(BIOS_INFO, "CPU: %s.\n", processor_name); |
| 550 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 551 | /* Setup MTRRs based on physical address size */ |
| 552 | cpuid_regs = cpuid(0x80000008); |
| 553 | x86_setup_fixed_mtrrs(); |
| 554 | x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2); |
| 555 | x86_mtrr_check(); |
| 556 | |
| 557 | /* Setup Page Attribute Tables (PAT) */ |
| 558 | // TODO set up PAT |
| 559 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 560 | /* Enable the local cpu apics */ |
| 561 | enable_lapic_tpr(); |
| 562 | setup_lapic(); |
| 563 | |
Marc Jones | 5986eda | 2012-10-25 09:37:19 -0600 | [diff] [blame] | 564 | /* Enable virtualization if enabled in CMOS */ |
| 565 | enable_vmx(); |
| 566 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 567 | /* Configure C States */ |
| 568 | configure_c_states(); |
| 569 | |
| 570 | /* Configure Enhanced SpeedStep and Thermal Sensors */ |
| 571 | configure_misc(); |
| 572 | |
Duncan Laurie | 5563211 | 2012-07-16 12:19:00 -0700 | [diff] [blame] | 573 | /* Thermal throttle activation offset */ |
| 574 | configure_thermal_target(); |
| 575 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 576 | /* Enable Direct Cache Access */ |
| 577 | configure_dca_cap(); |
| 578 | |
| 579 | /* Set energy policy */ |
| 580 | set_energy_perf_bias(ENERGY_POLICY_NORMAL); |
| 581 | |
| 582 | /* Set Max Ratio */ |
| 583 | set_max_ratio(); |
| 584 | |
| 585 | /* Enable Turbo */ |
| 586 | enable_turbo(); |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 587 | |
| 588 | /* Start up extra cores */ |
| 589 | intel_cores_init(cpu); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 590 | } |
| 591 | |
| 592 | static struct device_operations cpu_dev_ops = { |
| 593 | .init = model_206ax_init, |
| 594 | }; |
| 595 | |
| 596 | static struct cpu_device_id cpu_table[] = { |
| 597 | { X86_VENDOR_INTEL, 0x206a0 }, /* Intel Sandybridge */ |
| 598 | { X86_VENDOR_INTEL, 0x206a6 }, /* Intel Sandybridge D1 */ |
| 599 | { X86_VENDOR_INTEL, 0x206a7 }, /* Intel Sandybridge D2/J1 */ |
Stefan Reinauer | 08067ba | 2012-10-15 13:47:04 -0700 | [diff] [blame] | 600 | { X86_VENDOR_INTEL, 0x306a0 }, /* Intel IvyBridge */ |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 601 | { X86_VENDOR_INTEL, 0x306a2 }, /* Intel IvyBridge */ |
| 602 | { X86_VENDOR_INTEL, 0x306a4 }, /* Intel IvyBridge */ |
| 603 | { X86_VENDOR_INTEL, 0x306a5 }, /* Intel IvyBridge */ |
| 604 | { X86_VENDOR_INTEL, 0x306a6 }, /* Intel IvyBridge */ |
| 605 | { X86_VENDOR_INTEL, 0x306a8 }, /* Intel IvyBridge */ |
| 606 | { X86_VENDOR_INTEL, 0x306a9 }, /* Intel IvyBridge */ |
| 607 | { 0, 0 }, |
| 608 | }; |
| 609 | |
| 610 | static const struct cpu_driver driver __cpu_driver = { |
| 611 | .ops = &cpu_dev_ops, |
| 612 | .id_table = cpu_table, |
| 613 | .cstates = cstate_map, |
| 614 | }; |