blob: 33ad1e79aea8de76b42318a4f7e92e92beb0fc5b [file] [log] [blame]
Stefan Reinauer5c554632012-04-04 00:09:50 +02001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2009 coresystems GmbH
5 * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of
10 * the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Stefan Reinauer5c554632012-04-04 00:09:50 +020016 */
17
Arthur Heymansedbf5d92018-01-25 20:03:42 +010018#include <assert.h>
Stefan Reinauer5c554632012-04-04 00:09:50 +020019#include <console/console.h>
20#include <device/device.h>
Stefan Reinauer5c554632012-04-04 00:09:50 +020021#include <string.h>
22#include <arch/acpi.h>
Subrata Banik53b08c32018-12-10 14:11:35 +053023#include <arch/cpu.h>
Stefan Reinauer5c554632012-04-04 00:09:50 +020024#include <cpu/cpu.h>
25#include <cpu/x86/mtrr.h>
26#include <cpu/x86/msr.h>
27#include <cpu/x86/lapic.h>
Arthur Heymansedbf5d92018-01-25 20:03:42 +010028#include <cpu/x86/mp.h>
Stefan Reinauer5c554632012-04-04 00:09:50 +020029#include <cpu/intel/microcode.h>
30#include <cpu/intel/speedstep.h>
31#include <cpu/intel/turbo.h>
32#include <cpu/x86/cache.h>
33#include <cpu/x86/name.h>
34#include <pc80/mc146818rtc.h>
Stefan Reinauer5c554632012-04-04 00:09:50 +020035#include "model_206ax.h"
Duncan Laurie55632112012-07-16 12:19:00 -070036#include "chip.h"
Vladimir Serbinenkoc16e9dfa2015-05-29 16:18:01 +020037#include <cpu/intel/smm/gen1/smi.h>
Matt DeVilliered6fe2f2016-12-14 16:12:43 -060038#include <cpu/intel/common/common.h>
Vladimir Serbinenkoc16e9dfa2015-05-29 16:18:01 +020039
Stefan Reinauer5c554632012-04-04 00:09:50 +020040/*
Martin Roth4c3ab732013-07-08 16:23:54 -060041 * List of supported C-states in this processor
Stefan Reinauer5c554632012-04-04 00:09:50 +020042 *
43 * Latencies are typical worst-case package exit time in uS
44 * taken from the SandyBridge BIOS specification.
45 */
46static acpi_cstate_t cstate_map[] = {
47 { /* 0: C0 */
Lee Leahy9d62e7e2017-03-15 17:40:50 -070048 }, { /* 1: C1 */
Stefan Reinauer5c554632012-04-04 00:09:50 +020049 .latency = 1,
50 .power = 1000,
51 .resource = {
52 .addrl = 0x00, /* MWAIT State 0 */
53 .space_id = ACPI_ADDRESS_SPACE_FIXED,
54 .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
55 .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
56 .resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
57 }
58 },
59 { /* 2: C1E */
60 .latency = 1,
61 .power = 1000,
62 .resource = {
63 .addrl = 0x01, /* MWAIT State 0 Sub-state 1 */
64 .space_id = ACPI_ADDRESS_SPACE_FIXED,
65 .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
66 .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
67 .resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
68 }
69 },
70 { /* 3: C3 */
71 .latency = 63,
72 .power = 500,
73 .resource = {
74 .addrl = 0x10, /* MWAIT State 1 */
75 .space_id = ACPI_ADDRESS_SPACE_FIXED,
76 .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
77 .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
78 .resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
79 }
80 },
81 { /* 4: C6 */
82 .latency = 87,
83 .power = 350,
84 .resource = {
85 .addrl = 0x20, /* MWAIT State 2 */
86 .space_id = ACPI_ADDRESS_SPACE_FIXED,
87 .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
88 .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
89 .resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
90 }
91 },
92 { /* 5: C7 */
93 .latency = 90,
94 .power = 200,
95 .resource = {
96 .addrl = 0x30, /* MWAIT State 3 */
97 .space_id = ACPI_ADDRESS_SPACE_FIXED,
98 .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
99 .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
100 .resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
101 }
102 },
103 { /* 6: C7S */
104 .latency = 90,
105 .power = 200,
106 .resource = {
107 .addrl = 0x31, /* MWAIT State 3 Sub-state 1 */
108 .space_id = ACPI_ADDRESS_SPACE_FIXED,
109 .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
110 .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
111 .resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
112 }
113 },
114 { 0 }
115};
116
Stefan Reinauer5c554632012-04-04 00:09:50 +0200117/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
118static const u8 power_limit_time_sec_to_msr[] = {
119 [0] = 0x00,
120 [1] = 0x0a,
121 [2] = 0x0b,
122 [3] = 0x4b,
123 [4] = 0x0c,
124 [5] = 0x2c,
125 [6] = 0x4c,
126 [7] = 0x6c,
127 [8] = 0x0d,
128 [10] = 0x2d,
129 [12] = 0x4d,
130 [14] = 0x6d,
131 [16] = 0x0e,
132 [20] = 0x2e,
133 [24] = 0x4e,
134 [28] = 0x6e,
135 [32] = 0x0f,
136 [40] = 0x2f,
137 [48] = 0x4f,
138 [56] = 0x6f,
139 [64] = 0x10,
140 [80] = 0x30,
141 [96] = 0x50,
142 [112] = 0x70,
143 [128] = 0x11,
144};
145
146/* Convert POWER_LIMIT_1_TIME MSR value to seconds */
147static const u8 power_limit_time_msr_to_sec[] = {
148 [0x00] = 0,
149 [0x0a] = 1,
150 [0x0b] = 2,
151 [0x4b] = 3,
152 [0x0c] = 4,
153 [0x2c] = 5,
154 [0x4c] = 6,
155 [0x6c] = 7,
156 [0x0d] = 8,
157 [0x2d] = 10,
158 [0x4d] = 12,
159 [0x6d] = 14,
160 [0x0e] = 16,
161 [0x2e] = 20,
162 [0x4e] = 24,
163 [0x6e] = 28,
164 [0x0f] = 32,
165 [0x2f] = 40,
166 [0x4f] = 48,
167 [0x6f] = 56,
168 [0x10] = 64,
169 [0x30] = 80,
170 [0x50] = 96,
171 [0x70] = 112,
172 [0x11] = 128,
173};
174
Duncan Laurie77dbbac2012-06-25 09:51:59 -0700175int cpu_config_tdp_levels(void)
176{
177 msr_t platform_info;
178
179 /* Minimum CPU revision */
180 if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID)
181 return 0;
182
183 /* Bits 34:33 indicate how many levels supported */
184 platform_info = rdmsr(MSR_PLATFORM_INFO);
185 return (platform_info.hi >> 1) & 3;
186}
187
Stefan Reinauer5c554632012-04-04 00:09:50 +0200188/*
189 * Configure processor power limits if possible
190 * This must be done AFTER set of BIOS_RESET_CPL
191 */
192void set_power_limits(u8 power_limit_1_time)
193{
194 msr_t msr = rdmsr(MSR_PLATFORM_INFO);
195 msr_t limit;
Lee Leahy73a28942017-03-15 17:52:06 -0700196 unsigned int power_unit;
197 unsigned int tdp, min_power, max_power, max_time;
Stefan Reinauer5c554632012-04-04 00:09:50 +0200198 u8 power_limit_1_val;
199
Edward O'Callaghan5cfef132014-08-03 20:00:47 +1000200 if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr))
Stefan Reinauer5c554632012-04-04 00:09:50 +0200201 return;
202
203 if (!(msr.lo & PLATFORM_INFO_SET_TDP))
204 return;
205
206 /* Get units */
207 msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
208 power_unit = 2 << ((msr.lo & 0xf) - 1);
209
210 /* Get power defaults for this SKU */
211 msr = rdmsr(MSR_PKG_POWER_SKU);
212 tdp = msr.lo & 0x7fff;
213 min_power = (msr.lo >> 16) & 0x7fff;
214 max_power = msr.hi & 0x7fff;
215 max_time = (msr.hi >> 16) & 0x7f;
216
217 printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit);
218
219 if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time)
220 power_limit_1_time = power_limit_time_msr_to_sec[max_time];
221
222 if (min_power > 0 && tdp < min_power)
223 tdp = min_power;
224
225 if (max_power > 0 && tdp > max_power)
226 tdp = max_power;
227
228 power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time];
229
230 /* Set long term power limit to TDP */
231 limit.lo = 0;
232 limit.lo |= tdp & PKG_POWER_LIMIT_MASK;
233 limit.lo |= PKG_POWER_LIMIT_EN;
234 limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
235 PKG_POWER_LIMIT_TIME_SHIFT;
236
237 /* Set short term power limit to 1.25 * TDP */
238 limit.hi = 0;
239 limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK;
240 limit.hi |= PKG_POWER_LIMIT_EN;
241 /* Power limit 2 time is only programmable on SNB EP/EX */
242
243 wrmsr(MSR_PKG_POWER_LIMIT, limit);
Duncan Laurie77dbbac2012-06-25 09:51:59 -0700244
245 /* Use nominal TDP values for CPUs with configurable TDP */
246 if (cpu_config_tdp_levels()) {
247 msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
248 limit.hi = 0;
249 limit.lo = msr.lo & 0xff;
250 wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit);
251 }
Stefan Reinauer5c554632012-04-04 00:09:50 +0200252}
253
254static void configure_c_states(void)
255{
256 msr_t msr;
257
Elyes HAOUAS4e6b7902018-10-02 08:44:47 +0200258 msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);
Stefan Reinauer5c554632012-04-04 00:09:50 +0200259 msr.lo |= (1 << 28); // C1 Auto Undemotion Enable
260 msr.lo |= (1 << 27); // C3 Auto Undemotion Enable
261 msr.lo |= (1 << 26); // C1 Auto Demotion Enable
262 msr.lo |= (1 << 25); // C3 Auto Demotion Enable
263 msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection
264 msr.lo |= 7; // No package C-state limit
Elyes HAOUAS4e6b7902018-10-02 08:44:47 +0200265 wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
Stefan Reinauer5c554632012-04-04 00:09:50 +0200266
Patrick Georgi644e83b2013-02-09 15:35:30 +0100267 msr = rdmsr(MSR_PMG_IO_CAPTURE_ADDR);
Stefan Reinauer5c554632012-04-04 00:09:50 +0200268 msr.lo &= ~0x7ffff;
269 msr.lo |= (PMB0_BASE + 4); // LVL_2 base address
270 msr.lo |= (2 << 16); // CST Range: C7 is max C-state
Patrick Georgi644e83b2013-02-09 15:35:30 +0100271 wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr);
Stefan Reinauer5c554632012-04-04 00:09:50 +0200272
273 msr = rdmsr(MSR_MISC_PWR_MGMT);
274 msr.lo &= ~(1 << 0); // Enable P-state HW_ALL coordination
275 wrmsr(MSR_MISC_PWR_MGMT, msr);
276
277 msr = rdmsr(MSR_POWER_CTL);
278 msr.lo |= (1 << 18); // Enable Energy Perf Bias MSR 0x1b0
279 msr.lo |= (1 << 1); // C1E Enable
280 msr.lo |= (1 << 0); // Bi-directional PROCHOT#
281 wrmsr(MSR_POWER_CTL, msr);
282
283 /* C3 Interrupt Response Time Limit */
284 msr.hi = 0;
285 msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;
286 wrmsr(MSR_PKGC3_IRTL, msr);
287
288 /* C6 Interrupt Response Time Limit */
289 msr.hi = 0;
290 msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68;
291 wrmsr(MSR_PKGC6_IRTL, msr);
292
293 /* C7 Interrupt Response Time Limit */
294 msr.hi = 0;
295 msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D;
296 wrmsr(MSR_PKGC7_IRTL, msr);
297
298 /* Primary Plane Current Limit */
299 msr = rdmsr(MSR_PP0_CURRENT_CONFIG);
300 msr.lo &= ~0x1fff;
301 msr.lo |= PP0_CURRENT_LIMIT;
302 wrmsr(MSR_PP0_CURRENT_CONFIG, msr);
303
304 /* Secondary Plane Current Limit */
305 msr = rdmsr(MSR_PP1_CURRENT_CONFIG);
306 msr.lo &= ~0x1fff;
Duncan Laurie4e4320f2012-06-25 09:53:58 -0700307 if (cpuid_eax(1) >= 0x30600)
308 msr.lo |= PP1_CURRENT_LIMIT_IVB;
309 else
310 msr.lo |= PP1_CURRENT_LIMIT_SNB;
Stefan Reinauer5c554632012-04-04 00:09:50 +0200311 wrmsr(MSR_PP1_CURRENT_CONFIG, msr);
312}
313
Duncan Laurie55632112012-07-16 12:19:00 -0700314static void configure_thermal_target(void)
315{
316 struct cpu_intel_model_206ax_config *conf;
Edward O'Callaghan2c9d2cf2014-10-27 23:29:29 +1100317 struct device *lapic;
Duncan Laurie55632112012-07-16 12:19:00 -0700318 msr_t msr;
319
320 /* Find pointer to CPU configuration */
321 lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
322 if (!lapic || !lapic->chip_info)
323 return;
324 conf = lapic->chip_info;
325
Martin Roth4c3ab732013-07-08 16:23:54 -0600326 /* Set TCC activation offset if supported */
Duncan Laurie55632112012-07-16 12:19:00 -0700327 msr = rdmsr(MSR_PLATFORM_INFO);
328 if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
329 msr = rdmsr(MSR_TEMPERATURE_TARGET);
330 msr.lo &= ~(0xf << 24); /* Bits 27:24 */
331 msr.lo |= (conf->tcc_offset & 0xf) << 24;
332 wrmsr(MSR_TEMPERATURE_TARGET, msr);
333 }
334}
335
Stefan Reinauer5c554632012-04-04 00:09:50 +0200336static void configure_misc(void)
337{
338 msr_t msr;
339
340 msr = rdmsr(IA32_MISC_ENABLE);
341 msr.lo |= (1 << 0); /* Fast String enable */
Lee Leahy7b5f12b92017-03-15 17:16:59 -0700342 msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
Stefan Reinauer5c554632012-04-04 00:09:50 +0200343 msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
344 wrmsr(IA32_MISC_ENABLE, msr);
345
346 /* Disable Thermal interrupts */
347 msr.lo = 0;
348 msr.hi = 0;
349 wrmsr(IA32_THERM_INTERRUPT, msr);
350
351 /* Enable package critical interrupt only */
352 msr.lo = 1 << 4;
353 msr.hi = 0;
354 wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
355}
356
357static void enable_lapic_tpr(void)
358{
359 msr_t msr;
360
361 msr = rdmsr(MSR_PIC_MSG_CONTROL);
362 msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */
363 wrmsr(MSR_PIC_MSG_CONTROL, msr);
364}
365
366static void configure_dca_cap(void)
367{
Subrata Banik53b08c32018-12-10 14:11:35 +0530368 uint32_t feature_flag;
Stefan Reinauer5c554632012-04-04 00:09:50 +0200369 msr_t msr;
370
371 /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
Subrata Banik53b08c32018-12-10 14:11:35 +0530372 feature_flag = cpu_get_feature_flags_ecx();
373 if (feature_flag & CPUID_DCA) {
Stefan Reinauer5c554632012-04-04 00:09:50 +0200374 msr = rdmsr(IA32_PLATFORM_DCA_CAP);
375 msr.lo |= 1;
376 wrmsr(IA32_PLATFORM_DCA_CAP, msr);
377 }
378}
379
380static void set_max_ratio(void)
381{
Duncan Laurie77dbbac2012-06-25 09:51:59 -0700382 msr_t msr, perf_ctl;
Stefan Reinauer5c554632012-04-04 00:09:50 +0200383
Duncan Laurie77dbbac2012-06-25 09:51:59 -0700384 perf_ctl.hi = 0;
385
386 /* Check for configurable TDP option */
387 if (cpu_config_tdp_levels()) {
388 /* Set to nominal TDP ratio */
389 msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
390 perf_ctl.lo = (msr.lo & 0xff) << 8;
391 } else {
392 /* Platform Info bits 15:8 give max ratio */
393 msr = rdmsr(MSR_PLATFORM_INFO);
394 perf_ctl.lo = msr.lo & 0xff00;
395 }
396 wrmsr(IA32_PERF_CTL, perf_ctl);
Stefan Reinauer5c554632012-04-04 00:09:50 +0200397
398 printk(BIOS_DEBUG, "model_x06ax: frequency set to %d\n",
Duncan Laurie77dbbac2012-06-25 09:51:59 -0700399 ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK);
Stefan Reinauer5c554632012-04-04 00:09:50 +0200400}
401
402static void set_energy_perf_bias(u8 policy)
403{
404 msr_t msr;
405
406 /* Energy Policy is bits 3:0 */
Elyes HAOUAS419bfbc2018-10-01 08:47:51 +0200407 msr = rdmsr(IA32_ENERGY_PERF_BIAS);
Stefan Reinauer5c554632012-04-04 00:09:50 +0200408 msr.lo &= ~0xf;
409 msr.lo |= policy & 0xf;
Elyes HAOUAS419bfbc2018-10-01 08:47:51 +0200410 wrmsr(IA32_ENERGY_PERF_BIAS, msr);
Stefan Reinauer5c554632012-04-04 00:09:50 +0200411
412 printk(BIOS_DEBUG, "model_x06ax: energy policy set to %u\n",
413 policy);
414}
415
416static void configure_mca(void)
417{
418 msr_t msr;
419 int i;
Dan Elkoubydfaff4d2018-09-03 18:34:07 +0300420 int num_banks;
421
422 msr = rdmsr(IA32_MCG_CAP);
423 num_banks = msr.lo & 0xff;
Stefan Reinauer5c554632012-04-04 00:09:50 +0200424
425 msr.lo = msr.hi = 0;
426 /* This should only be done on a cold boot */
Dan Elkoubydfaff4d2018-09-03 18:34:07 +0300427 for (i = 0; i < num_banks; i++)
Stefan Reinauer5c554632012-04-04 00:09:50 +0200428 wrmsr(IA32_MC0_STATUS + (i * 4), msr);
429}
430
Patrick Rudolph9e1b9b52018-07-27 17:25:05 +0200431static void model_206ax_report(void)
432{
433 static const char *const mode[] = {"NOT ", ""};
Patrick Rudolph9e1b9b52018-07-27 17:25:05 +0200434 char processor_name[49];
435 int vt, txt, aes;
Subrata Banik53b08c32018-12-10 14:11:35 +0530436 uint32_t cpu_id, cpu_feature_flag;
Patrick Rudolph9e1b9b52018-07-27 17:25:05 +0200437
438 /* Print processor name */
439 fill_processor_name(processor_name);
440 printk(BIOS_INFO, "CPU: %s.\n", processor_name);
441
442 /* Print platform ID */
443 printk(BIOS_INFO, "CPU: platform id %x\n", get_platform_id());
444
445 /* CPUID and features */
Subrata Banik53b08c32018-12-10 14:11:35 +0530446 cpu_id = cpu_get_cpuid();
447 printk(BIOS_INFO, "CPU: cpuid(1) 0x%x\n", cpu_id);
448
449 cpu_feature_flag = cpu_get_feature_flags_ecx();
450 aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0;
451 txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0;
452 vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0;
Patrick Rudolph9e1b9b52018-07-27 17:25:05 +0200453 printk(BIOS_INFO, "CPU: AES %ssupported\n", mode[aes]);
454 printk(BIOS_INFO, "CPU: TXT %ssupported\n", mode[txt]);
455 printk(BIOS_INFO, "CPU: VT %ssupported\n", mode[vt]);
456}
457
Edward O'Callaghan2c9d2cf2014-10-27 23:29:29 +1100458static void model_206ax_init(struct device *cpu)
Stefan Reinauer5c554632012-04-04 00:09:50 +0200459{
Stefan Reinauer5c554632012-04-04 00:09:50 +0200460
461 /* Turn on caching if we haven't already */
462 x86_enable_cache();
463
Stefan Reinauer5c554632012-04-04 00:09:50 +0200464 /* Clear out pending MCEs */
465 configure_mca();
466
Patrick Rudolph9e1b9b52018-07-27 17:25:05 +0200467 /* Print infos */
468 model_206ax_report();
Patrick Rudolph74203de2017-11-20 11:57:01 +0100469
Stefan Reinauer5c554632012-04-04 00:09:50 +0200470 /* Setup Page Attribute Tables (PAT) */
471 // TODO set up PAT
472
Elyes HAOUASd6e96862016-08-21 10:12:15 +0200473 /* Enable the local CPU APICs */
Stefan Reinauer5c554632012-04-04 00:09:50 +0200474 enable_lapic_tpr();
475 setup_lapic();
476
Matt DeVilliered6fe2f2016-12-14 16:12:43 -0600477 /* Set virtualization based on Kconfig option */
Matt DeVillierf9aed652018-12-15 15:57:33 -0600478 set_vmx_and_lock();
Marc Jones5986eda2012-10-25 09:37:19 -0600479
Stefan Reinauer5c554632012-04-04 00:09:50 +0200480 /* Configure C States */
481 configure_c_states();
482
483 /* Configure Enhanced SpeedStep and Thermal Sensors */
484 configure_misc();
485
Duncan Laurie55632112012-07-16 12:19:00 -0700486 /* Thermal throttle activation offset */
487 configure_thermal_target();
488
Stefan Reinauer5c554632012-04-04 00:09:50 +0200489 /* Enable Direct Cache Access */
490 configure_dca_cap();
491
492 /* Set energy policy */
493 set_energy_perf_bias(ENERGY_POLICY_NORMAL);
494
495 /* Set Max Ratio */
496 set_max_ratio();
497
498 /* Enable Turbo */
499 enable_turbo();
Arthur Heymansedbf5d92018-01-25 20:03:42 +0100500}
Sven Schnelle51676b12012-07-29 19:18:03 +0200501
Arthur Heymansedbf5d92018-01-25 20:03:42 +0100502/* MP initialization support. */
503static const void *microcode_patch;
504
505static void pre_mp_init(void)
506{
507 /* Setup MTRRs based on physical address size. */
508 x86_setup_mtrrs_with_detect();
509 x86_mtrr_check();
510}
511
512static int get_cpu_count(void)
513{
514 msr_t msr;
515 int num_threads;
516 int num_cores;
517
518 msr = rdmsr(CORE_THREAD_COUNT_MSR);
519 num_threads = (msr.lo >> 0) & 0xffff;
520 num_cores = (msr.lo >> 16) & 0xffff;
521 printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n",
522 num_cores, num_threads);
523
524 return num_threads;
525}
526
527static void get_microcode_info(const void **microcode, int *parallel)
528{
529 microcode_patch = intel_microcode_find();
530 *microcode = microcode_patch;
531 *parallel = 1;
532}
533
534static void per_cpu_smm_trigger(void)
535{
536 /* Relocate the SMM handler. */
537 smm_relocate();
538
539 /* After SMM relocation a 2nd microcode load is required. */
540 intel_microcode_load_unlocked(microcode_patch);
541}
542
543static void post_mp_init(void)
544{
545 /* Now that all APs have been relocated as well as the BSP let SMIs
546 * start flowing. */
547 southbridge_smm_init();
548
549 /* Lock down the SMRAM space. */
550 smm_lock();
551}
552
553
554static const struct mp_ops mp_ops = {
555 .pre_mp_init = pre_mp_init,
556 .get_cpu_count = get_cpu_count,
557 .get_smm_info = smm_info,
558 .get_microcode_info = get_microcode_info,
559 .pre_mp_smm_init = smm_initialize,
560 .per_cpu_smm_trigger = per_cpu_smm_trigger,
561 .relocation_handler = smm_relocation_handler,
562 .post_mp_init = post_mp_init,
563};
564
565void bsp_init_and_start_aps(struct bus *cpu_bus)
566{
567 if (mp_init_with_smm(cpu_bus, &mp_ops))
568 printk(BIOS_ERR, "MP initialization failure.\n");
Stefan Reinauer5c554632012-04-04 00:09:50 +0200569}
570
571static struct device_operations cpu_dev_ops = {
572 .init = model_206ax_init,
573};
574
Jonathan Neuschäfer8f06ce32017-11-20 01:56:44 +0100575static const struct cpu_device_id cpu_table[] = {
Stefan Reinauer5c554632012-04-04 00:09:50 +0200576 { X86_VENDOR_INTEL, 0x206a0 }, /* Intel Sandybridge */
577 { X86_VENDOR_INTEL, 0x206a6 }, /* Intel Sandybridge D1 */
578 { X86_VENDOR_INTEL, 0x206a7 }, /* Intel Sandybridge D2/J1 */
Stefan Reinauer08067ba2012-10-15 13:47:04 -0700579 { X86_VENDOR_INTEL, 0x306a0 }, /* Intel IvyBridge */
Stefan Reinauer5c554632012-04-04 00:09:50 +0200580 { X86_VENDOR_INTEL, 0x306a2 }, /* Intel IvyBridge */
581 { X86_VENDOR_INTEL, 0x306a4 }, /* Intel IvyBridge */
582 { X86_VENDOR_INTEL, 0x306a5 }, /* Intel IvyBridge */
583 { X86_VENDOR_INTEL, 0x306a6 }, /* Intel IvyBridge */
584 { X86_VENDOR_INTEL, 0x306a8 }, /* Intel IvyBridge */
585 { X86_VENDOR_INTEL, 0x306a9 }, /* Intel IvyBridge */
586 { 0, 0 },
587};
588
589static const struct cpu_driver driver __cpu_driver = {
590 .ops = &cpu_dev_ops,
591 .id_table = cpu_table,
592 .cstates = cstate_map,
593};