Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <console/console.h> |
| 19 | #include <device/device.h> |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 20 | #include <arch/acpi.h> |
Subrata Banik | 53b08c3 | 2018-12-10 14:11:35 +0530 | [diff] [blame] | 21 | #include <arch/cpu.h> |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 22 | #include <cpu/cpu.h> |
| 23 | #include <cpu/x86/mtrr.h> |
| 24 | #include <cpu/x86/msr.h> |
| 25 | #include <cpu/x86/lapic.h> |
Arthur Heymans | edbf5d9 | 2018-01-25 20:03:42 +0100 | [diff] [blame] | 26 | #include <cpu/x86/mp.h> |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 27 | #include <cpu/intel/microcode.h> |
| 28 | #include <cpu/intel/speedstep.h> |
| 29 | #include <cpu/intel/turbo.h> |
| 30 | #include <cpu/x86/cache.h> |
| 31 | #include <cpu/x86/name.h> |
| 32 | #include <pc80/mc146818rtc.h> |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 33 | #include "model_206ax.h" |
Duncan Laurie | 5563211 | 2012-07-16 12:19:00 -0700 | [diff] [blame] | 34 | #include "chip.h" |
Kyösti Mälkki | f091f4d | 2019-08-14 03:49:21 +0300 | [diff] [blame^] | 35 | #include <cpu/intel/smm_reloc.h> |
Matt DeVillier | ed6fe2f | 2016-12-14 16:12:43 -0600 | [diff] [blame] | 36 | #include <cpu/intel/common/common.h> |
Vladimir Serbinenko | c16e9dfa | 2015-05-29 16:18:01 +0200 | [diff] [blame] | 37 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 38 | /* |
Martin Roth | 4c3ab73 | 2013-07-08 16:23:54 -0600 | [diff] [blame] | 39 | * List of supported C-states in this processor |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 40 | * |
| 41 | * Latencies are typical worst-case package exit time in uS |
| 42 | * taken from the SandyBridge BIOS specification. |
| 43 | */ |
| 44 | static acpi_cstate_t cstate_map[] = { |
| 45 | { /* 0: C0 */ |
Lee Leahy | 9d62e7e | 2017-03-15 17:40:50 -0700 | [diff] [blame] | 46 | }, { /* 1: C1 */ |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 47 | .latency = 1, |
| 48 | .power = 1000, |
| 49 | .resource = { |
| 50 | .addrl = 0x00, /* MWAIT State 0 */ |
| 51 | .space_id = ACPI_ADDRESS_SPACE_FIXED, |
| 52 | .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, |
| 53 | .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, |
Elyes HAOUAS | 8ee161d | 2019-03-03 12:49:56 +0100 | [diff] [blame] | 54 | .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 55 | } |
| 56 | }, |
| 57 | { /* 2: C1E */ |
| 58 | .latency = 1, |
| 59 | .power = 1000, |
| 60 | .resource = { |
| 61 | .addrl = 0x01, /* MWAIT State 0 Sub-state 1 */ |
| 62 | .space_id = ACPI_ADDRESS_SPACE_FIXED, |
| 63 | .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, |
| 64 | .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, |
Elyes HAOUAS | 8ee161d | 2019-03-03 12:49:56 +0100 | [diff] [blame] | 65 | .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 66 | } |
| 67 | }, |
| 68 | { /* 3: C3 */ |
| 69 | .latency = 63, |
| 70 | .power = 500, |
| 71 | .resource = { |
| 72 | .addrl = 0x10, /* MWAIT State 1 */ |
| 73 | .space_id = ACPI_ADDRESS_SPACE_FIXED, |
| 74 | .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, |
| 75 | .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, |
Elyes HAOUAS | 8ee161d | 2019-03-03 12:49:56 +0100 | [diff] [blame] | 76 | .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 77 | } |
| 78 | }, |
| 79 | { /* 4: C6 */ |
| 80 | .latency = 87, |
| 81 | .power = 350, |
| 82 | .resource = { |
| 83 | .addrl = 0x20, /* MWAIT State 2 */ |
| 84 | .space_id = ACPI_ADDRESS_SPACE_FIXED, |
| 85 | .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, |
| 86 | .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, |
Elyes HAOUAS | 8ee161d | 2019-03-03 12:49:56 +0100 | [diff] [blame] | 87 | .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 88 | } |
| 89 | }, |
| 90 | { /* 5: C7 */ |
| 91 | .latency = 90, |
| 92 | .power = 200, |
| 93 | .resource = { |
| 94 | .addrl = 0x30, /* MWAIT State 3 */ |
| 95 | .space_id = ACPI_ADDRESS_SPACE_FIXED, |
| 96 | .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, |
| 97 | .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, |
Elyes HAOUAS | 8ee161d | 2019-03-03 12:49:56 +0100 | [diff] [blame] | 98 | .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 99 | } |
| 100 | }, |
| 101 | { /* 6: C7S */ |
| 102 | .latency = 90, |
| 103 | .power = 200, |
| 104 | .resource = { |
| 105 | .addrl = 0x31, /* MWAIT State 3 Sub-state 1 */ |
| 106 | .space_id = ACPI_ADDRESS_SPACE_FIXED, |
| 107 | .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, |
| 108 | .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, |
Elyes HAOUAS | 8ee161d | 2019-03-03 12:49:56 +0100 | [diff] [blame] | 109 | .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 110 | } |
| 111 | }, |
| 112 | { 0 } |
| 113 | }; |
| 114 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 115 | /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ |
| 116 | static const u8 power_limit_time_sec_to_msr[] = { |
| 117 | [0] = 0x00, |
| 118 | [1] = 0x0a, |
| 119 | [2] = 0x0b, |
| 120 | [3] = 0x4b, |
| 121 | [4] = 0x0c, |
| 122 | [5] = 0x2c, |
| 123 | [6] = 0x4c, |
| 124 | [7] = 0x6c, |
| 125 | [8] = 0x0d, |
| 126 | [10] = 0x2d, |
| 127 | [12] = 0x4d, |
| 128 | [14] = 0x6d, |
| 129 | [16] = 0x0e, |
| 130 | [20] = 0x2e, |
| 131 | [24] = 0x4e, |
| 132 | [28] = 0x6e, |
| 133 | [32] = 0x0f, |
| 134 | [40] = 0x2f, |
| 135 | [48] = 0x4f, |
| 136 | [56] = 0x6f, |
| 137 | [64] = 0x10, |
| 138 | [80] = 0x30, |
| 139 | [96] = 0x50, |
| 140 | [112] = 0x70, |
| 141 | [128] = 0x11, |
| 142 | }; |
| 143 | |
| 144 | /* Convert POWER_LIMIT_1_TIME MSR value to seconds */ |
| 145 | static const u8 power_limit_time_msr_to_sec[] = { |
| 146 | [0x00] = 0, |
| 147 | [0x0a] = 1, |
| 148 | [0x0b] = 2, |
| 149 | [0x4b] = 3, |
| 150 | [0x0c] = 4, |
| 151 | [0x2c] = 5, |
| 152 | [0x4c] = 6, |
| 153 | [0x6c] = 7, |
| 154 | [0x0d] = 8, |
| 155 | [0x2d] = 10, |
| 156 | [0x4d] = 12, |
| 157 | [0x6d] = 14, |
| 158 | [0x0e] = 16, |
| 159 | [0x2e] = 20, |
| 160 | [0x4e] = 24, |
| 161 | [0x6e] = 28, |
| 162 | [0x0f] = 32, |
| 163 | [0x2f] = 40, |
| 164 | [0x4f] = 48, |
| 165 | [0x6f] = 56, |
| 166 | [0x10] = 64, |
| 167 | [0x30] = 80, |
| 168 | [0x50] = 96, |
| 169 | [0x70] = 112, |
| 170 | [0x11] = 128, |
| 171 | }; |
| 172 | |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 173 | int cpu_config_tdp_levels(void) |
| 174 | { |
| 175 | msr_t platform_info; |
| 176 | |
| 177 | /* Minimum CPU revision */ |
| 178 | if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID) |
| 179 | return 0; |
| 180 | |
| 181 | /* Bits 34:33 indicate how many levels supported */ |
| 182 | platform_info = rdmsr(MSR_PLATFORM_INFO); |
| 183 | return (platform_info.hi >> 1) & 3; |
| 184 | } |
| 185 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 186 | /* |
| 187 | * Configure processor power limits if possible |
| 188 | * This must be done AFTER set of BIOS_RESET_CPL |
| 189 | */ |
| 190 | void set_power_limits(u8 power_limit_1_time) |
| 191 | { |
| 192 | msr_t msr = rdmsr(MSR_PLATFORM_INFO); |
| 193 | msr_t limit; |
Lee Leahy | 73a2894 | 2017-03-15 17:52:06 -0700 | [diff] [blame] | 194 | unsigned int power_unit; |
| 195 | unsigned int tdp, min_power, max_power, max_time; |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 196 | u8 power_limit_1_val; |
| 197 | |
Edward O'Callaghan | 5cfef13 | 2014-08-03 20:00:47 +1000 | [diff] [blame] | 198 | if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 199 | return; |
| 200 | |
| 201 | if (!(msr.lo & PLATFORM_INFO_SET_TDP)) |
| 202 | return; |
| 203 | |
| 204 | /* Get units */ |
| 205 | msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); |
| 206 | power_unit = 2 << ((msr.lo & 0xf) - 1); |
| 207 | |
| 208 | /* Get power defaults for this SKU */ |
| 209 | msr = rdmsr(MSR_PKG_POWER_SKU); |
| 210 | tdp = msr.lo & 0x7fff; |
| 211 | min_power = (msr.lo >> 16) & 0x7fff; |
| 212 | max_power = msr.hi & 0x7fff; |
| 213 | max_time = (msr.hi >> 16) & 0x7f; |
| 214 | |
| 215 | printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit); |
| 216 | |
| 217 | if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time) |
| 218 | power_limit_1_time = power_limit_time_msr_to_sec[max_time]; |
| 219 | |
| 220 | if (min_power > 0 && tdp < min_power) |
| 221 | tdp = min_power; |
| 222 | |
| 223 | if (max_power > 0 && tdp > max_power) |
| 224 | tdp = max_power; |
| 225 | |
| 226 | power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time]; |
| 227 | |
| 228 | /* Set long term power limit to TDP */ |
| 229 | limit.lo = 0; |
| 230 | limit.lo |= tdp & PKG_POWER_LIMIT_MASK; |
| 231 | limit.lo |= PKG_POWER_LIMIT_EN; |
| 232 | limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << |
| 233 | PKG_POWER_LIMIT_TIME_SHIFT; |
| 234 | |
| 235 | /* Set short term power limit to 1.25 * TDP */ |
| 236 | limit.hi = 0; |
| 237 | limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK; |
| 238 | limit.hi |= PKG_POWER_LIMIT_EN; |
| 239 | /* Power limit 2 time is only programmable on SNB EP/EX */ |
| 240 | |
| 241 | wrmsr(MSR_PKG_POWER_LIMIT, limit); |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 242 | |
| 243 | /* Use nominal TDP values for CPUs with configurable TDP */ |
| 244 | if (cpu_config_tdp_levels()) { |
| 245 | msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); |
| 246 | limit.hi = 0; |
| 247 | limit.lo = msr.lo & 0xff; |
| 248 | wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit); |
| 249 | } |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 250 | } |
| 251 | |
| 252 | static void configure_c_states(void) |
| 253 | { |
| 254 | msr_t msr; |
| 255 | |
Elyes HAOUAS | 4e6b790 | 2018-10-02 08:44:47 +0200 | [diff] [blame] | 256 | msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 257 | msr.lo |= (1 << 28); // C1 Auto Undemotion Enable |
| 258 | msr.lo |= (1 << 27); // C3 Auto Undemotion Enable |
| 259 | msr.lo |= (1 << 26); // C1 Auto Demotion Enable |
| 260 | msr.lo |= (1 << 25); // C3 Auto Demotion Enable |
| 261 | msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection |
| 262 | msr.lo |= 7; // No package C-state limit |
Elyes HAOUAS | 4e6b790 | 2018-10-02 08:44:47 +0200 | [diff] [blame] | 263 | wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 264 | |
Patrick Georgi | 644e83b | 2013-02-09 15:35:30 +0100 | [diff] [blame] | 265 | msr = rdmsr(MSR_PMG_IO_CAPTURE_ADDR); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 266 | msr.lo &= ~0x7ffff; |
| 267 | msr.lo |= (PMB0_BASE + 4); // LVL_2 base address |
| 268 | msr.lo |= (2 << 16); // CST Range: C7 is max C-state |
Patrick Georgi | 644e83b | 2013-02-09 15:35:30 +0100 | [diff] [blame] | 269 | wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 270 | |
| 271 | msr = rdmsr(MSR_MISC_PWR_MGMT); |
| 272 | msr.lo &= ~(1 << 0); // Enable P-state HW_ALL coordination |
| 273 | wrmsr(MSR_MISC_PWR_MGMT, msr); |
| 274 | |
| 275 | msr = rdmsr(MSR_POWER_CTL); |
| 276 | msr.lo |= (1 << 18); // Enable Energy Perf Bias MSR 0x1b0 |
| 277 | msr.lo |= (1 << 1); // C1E Enable |
| 278 | msr.lo |= (1 << 0); // Bi-directional PROCHOT# |
| 279 | wrmsr(MSR_POWER_CTL, msr); |
| 280 | |
| 281 | /* C3 Interrupt Response Time Limit */ |
| 282 | msr.hi = 0; |
| 283 | msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50; |
| 284 | wrmsr(MSR_PKGC3_IRTL, msr); |
| 285 | |
| 286 | /* C6 Interrupt Response Time Limit */ |
| 287 | msr.hi = 0; |
| 288 | msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68; |
| 289 | wrmsr(MSR_PKGC6_IRTL, msr); |
| 290 | |
| 291 | /* C7 Interrupt Response Time Limit */ |
| 292 | msr.hi = 0; |
| 293 | msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D; |
| 294 | wrmsr(MSR_PKGC7_IRTL, msr); |
| 295 | |
| 296 | /* Primary Plane Current Limit */ |
| 297 | msr = rdmsr(MSR_PP0_CURRENT_CONFIG); |
| 298 | msr.lo &= ~0x1fff; |
| 299 | msr.lo |= PP0_CURRENT_LIMIT; |
| 300 | wrmsr(MSR_PP0_CURRENT_CONFIG, msr); |
| 301 | |
| 302 | /* Secondary Plane Current Limit */ |
| 303 | msr = rdmsr(MSR_PP1_CURRENT_CONFIG); |
| 304 | msr.lo &= ~0x1fff; |
Duncan Laurie | 4e4320f | 2012-06-25 09:53:58 -0700 | [diff] [blame] | 305 | if (cpuid_eax(1) >= 0x30600) |
| 306 | msr.lo |= PP1_CURRENT_LIMIT_IVB; |
| 307 | else |
| 308 | msr.lo |= PP1_CURRENT_LIMIT_SNB; |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 309 | wrmsr(MSR_PP1_CURRENT_CONFIG, msr); |
| 310 | } |
| 311 | |
Duncan Laurie | 5563211 | 2012-07-16 12:19:00 -0700 | [diff] [blame] | 312 | static void configure_thermal_target(void) |
| 313 | { |
| 314 | struct cpu_intel_model_206ax_config *conf; |
Edward O'Callaghan | 2c9d2cf | 2014-10-27 23:29:29 +1100 | [diff] [blame] | 315 | struct device *lapic; |
Duncan Laurie | 5563211 | 2012-07-16 12:19:00 -0700 | [diff] [blame] | 316 | msr_t msr; |
| 317 | |
| 318 | /* Find pointer to CPU configuration */ |
| 319 | lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); |
| 320 | if (!lapic || !lapic->chip_info) |
| 321 | return; |
| 322 | conf = lapic->chip_info; |
| 323 | |
Martin Roth | 4c3ab73 | 2013-07-08 16:23:54 -0600 | [diff] [blame] | 324 | /* Set TCC activation offset if supported */ |
Duncan Laurie | 5563211 | 2012-07-16 12:19:00 -0700 | [diff] [blame] | 325 | msr = rdmsr(MSR_PLATFORM_INFO); |
| 326 | if ((msr.lo & (1 << 30)) && conf->tcc_offset) { |
| 327 | msr = rdmsr(MSR_TEMPERATURE_TARGET); |
| 328 | msr.lo &= ~(0xf << 24); /* Bits 27:24 */ |
| 329 | msr.lo |= (conf->tcc_offset & 0xf) << 24; |
| 330 | wrmsr(MSR_TEMPERATURE_TARGET, msr); |
| 331 | } |
| 332 | } |
| 333 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 334 | static void configure_misc(void) |
| 335 | { |
| 336 | msr_t msr; |
| 337 | |
| 338 | msr = rdmsr(IA32_MISC_ENABLE); |
| 339 | msr.lo |= (1 << 0); /* Fast String enable */ |
Lee Leahy | 7b5f12b9 | 2017-03-15 17:16:59 -0700 | [diff] [blame] | 340 | msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 341 | msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ |
| 342 | wrmsr(IA32_MISC_ENABLE, msr); |
| 343 | |
| 344 | /* Disable Thermal interrupts */ |
| 345 | msr.lo = 0; |
| 346 | msr.hi = 0; |
| 347 | wrmsr(IA32_THERM_INTERRUPT, msr); |
| 348 | |
| 349 | /* Enable package critical interrupt only */ |
| 350 | msr.lo = 1 << 4; |
| 351 | msr.hi = 0; |
| 352 | wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); |
| 353 | } |
| 354 | |
| 355 | static void enable_lapic_tpr(void) |
| 356 | { |
| 357 | msr_t msr; |
| 358 | |
| 359 | msr = rdmsr(MSR_PIC_MSG_CONTROL); |
| 360 | msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ |
| 361 | wrmsr(MSR_PIC_MSG_CONTROL, msr); |
| 362 | } |
| 363 | |
| 364 | static void configure_dca_cap(void) |
| 365 | { |
Subrata Banik | 53b08c3 | 2018-12-10 14:11:35 +0530 | [diff] [blame] | 366 | uint32_t feature_flag; |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 367 | msr_t msr; |
| 368 | |
| 369 | /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ |
Subrata Banik | 53b08c3 | 2018-12-10 14:11:35 +0530 | [diff] [blame] | 370 | feature_flag = cpu_get_feature_flags_ecx(); |
| 371 | if (feature_flag & CPUID_DCA) { |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 372 | msr = rdmsr(IA32_PLATFORM_DCA_CAP); |
| 373 | msr.lo |= 1; |
| 374 | wrmsr(IA32_PLATFORM_DCA_CAP, msr); |
| 375 | } |
| 376 | } |
| 377 | |
| 378 | static void set_max_ratio(void) |
| 379 | { |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 380 | msr_t msr, perf_ctl; |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 381 | |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 382 | perf_ctl.hi = 0; |
| 383 | |
| 384 | /* Check for configurable TDP option */ |
| 385 | if (cpu_config_tdp_levels()) { |
| 386 | /* Set to nominal TDP ratio */ |
| 387 | msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); |
| 388 | perf_ctl.lo = (msr.lo & 0xff) << 8; |
| 389 | } else { |
| 390 | /* Platform Info bits 15:8 give max ratio */ |
| 391 | msr = rdmsr(MSR_PLATFORM_INFO); |
| 392 | perf_ctl.lo = msr.lo & 0xff00; |
| 393 | } |
| 394 | wrmsr(IA32_PERF_CTL, perf_ctl); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 395 | |
| 396 | printk(BIOS_DEBUG, "model_x06ax: frequency set to %d\n", |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 397 | ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 398 | } |
| 399 | |
| 400 | static void set_energy_perf_bias(u8 policy) |
| 401 | { |
| 402 | msr_t msr; |
| 403 | |
| 404 | /* Energy Policy is bits 3:0 */ |
Elyes HAOUAS | 419bfbc | 2018-10-01 08:47:51 +0200 | [diff] [blame] | 405 | msr = rdmsr(IA32_ENERGY_PERF_BIAS); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 406 | msr.lo &= ~0xf; |
| 407 | msr.lo |= policy & 0xf; |
Elyes HAOUAS | 419bfbc | 2018-10-01 08:47:51 +0200 | [diff] [blame] | 408 | wrmsr(IA32_ENERGY_PERF_BIAS, msr); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 409 | |
| 410 | printk(BIOS_DEBUG, "model_x06ax: energy policy set to %u\n", |
| 411 | policy); |
| 412 | } |
| 413 | |
| 414 | static void configure_mca(void) |
| 415 | { |
| 416 | msr_t msr; |
| 417 | int i; |
Dan Elkouby | dfaff4d | 2018-09-03 18:34:07 +0300 | [diff] [blame] | 418 | int num_banks; |
| 419 | |
| 420 | msr = rdmsr(IA32_MCG_CAP); |
| 421 | num_banks = msr.lo & 0xff; |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 422 | |
| 423 | msr.lo = msr.hi = 0; |
| 424 | /* This should only be done on a cold boot */ |
Dan Elkouby | dfaff4d | 2018-09-03 18:34:07 +0300 | [diff] [blame] | 425 | for (i = 0; i < num_banks; i++) |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 426 | wrmsr(IA32_MC0_STATUS + (i * 4), msr); |
| 427 | } |
| 428 | |
Patrick Rudolph | 9e1b9b5 | 2018-07-27 17:25:05 +0200 | [diff] [blame] | 429 | static void model_206ax_report(void) |
| 430 | { |
| 431 | static const char *const mode[] = {"NOT ", ""}; |
Patrick Rudolph | 9e1b9b5 | 2018-07-27 17:25:05 +0200 | [diff] [blame] | 432 | char processor_name[49]; |
| 433 | int vt, txt, aes; |
Subrata Banik | 53b08c3 | 2018-12-10 14:11:35 +0530 | [diff] [blame] | 434 | uint32_t cpu_id, cpu_feature_flag; |
Patrick Rudolph | 9e1b9b5 | 2018-07-27 17:25:05 +0200 | [diff] [blame] | 435 | |
| 436 | /* Print processor name */ |
| 437 | fill_processor_name(processor_name); |
| 438 | printk(BIOS_INFO, "CPU: %s.\n", processor_name); |
| 439 | |
| 440 | /* Print platform ID */ |
| 441 | printk(BIOS_INFO, "CPU: platform id %x\n", get_platform_id()); |
| 442 | |
| 443 | /* CPUID and features */ |
Subrata Banik | 53b08c3 | 2018-12-10 14:11:35 +0530 | [diff] [blame] | 444 | cpu_id = cpu_get_cpuid(); |
| 445 | printk(BIOS_INFO, "CPU: cpuid(1) 0x%x\n", cpu_id); |
| 446 | |
| 447 | cpu_feature_flag = cpu_get_feature_flags_ecx(); |
| 448 | aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0; |
| 449 | txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0; |
| 450 | vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0; |
Patrick Rudolph | 9e1b9b5 | 2018-07-27 17:25:05 +0200 | [diff] [blame] | 451 | printk(BIOS_INFO, "CPU: AES %ssupported\n", mode[aes]); |
| 452 | printk(BIOS_INFO, "CPU: TXT %ssupported\n", mode[txt]); |
| 453 | printk(BIOS_INFO, "CPU: VT %ssupported\n", mode[vt]); |
| 454 | } |
| 455 | |
Edward O'Callaghan | 2c9d2cf | 2014-10-27 23:29:29 +1100 | [diff] [blame] | 456 | static void model_206ax_init(struct device *cpu) |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 457 | { |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 458 | |
| 459 | /* Turn on caching if we haven't already */ |
| 460 | x86_enable_cache(); |
| 461 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 462 | /* Clear out pending MCEs */ |
| 463 | configure_mca(); |
| 464 | |
Patrick Rudolph | 9e1b9b5 | 2018-07-27 17:25:05 +0200 | [diff] [blame] | 465 | /* Print infos */ |
| 466 | model_206ax_report(); |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 467 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 468 | /* Setup Page Attribute Tables (PAT) */ |
| 469 | // TODO set up PAT |
| 470 | |
Elyes HAOUAS | d6e9686 | 2016-08-21 10:12:15 +0200 | [diff] [blame] | 471 | /* Enable the local CPU APICs */ |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 472 | enable_lapic_tpr(); |
| 473 | setup_lapic(); |
| 474 | |
Matt DeVillier | ed6fe2f | 2016-12-14 16:12:43 -0600 | [diff] [blame] | 475 | /* Set virtualization based on Kconfig option */ |
Matt DeVillier | f9aed65 | 2018-12-15 15:57:33 -0600 | [diff] [blame] | 476 | set_vmx_and_lock(); |
Marc Jones | 5986eda | 2012-10-25 09:37:19 -0600 | [diff] [blame] | 477 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 478 | /* Configure C States */ |
| 479 | configure_c_states(); |
| 480 | |
| 481 | /* Configure Enhanced SpeedStep and Thermal Sensors */ |
| 482 | configure_misc(); |
| 483 | |
Duncan Laurie | 5563211 | 2012-07-16 12:19:00 -0700 | [diff] [blame] | 484 | /* Thermal throttle activation offset */ |
| 485 | configure_thermal_target(); |
| 486 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 487 | /* Enable Direct Cache Access */ |
| 488 | configure_dca_cap(); |
| 489 | |
| 490 | /* Set energy policy */ |
| 491 | set_energy_perf_bias(ENERGY_POLICY_NORMAL); |
| 492 | |
| 493 | /* Set Max Ratio */ |
| 494 | set_max_ratio(); |
| 495 | |
| 496 | /* Enable Turbo */ |
| 497 | enable_turbo(); |
Arthur Heymans | edbf5d9 | 2018-01-25 20:03:42 +0100 | [diff] [blame] | 498 | } |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 499 | |
Arthur Heymans | edbf5d9 | 2018-01-25 20:03:42 +0100 | [diff] [blame] | 500 | /* MP initialization support. */ |
| 501 | static const void *microcode_patch; |
| 502 | |
| 503 | static void pre_mp_init(void) |
| 504 | { |
| 505 | /* Setup MTRRs based on physical address size. */ |
| 506 | x86_setup_mtrrs_with_detect(); |
| 507 | x86_mtrr_check(); |
| 508 | } |
| 509 | |
| 510 | static int get_cpu_count(void) |
| 511 | { |
| 512 | msr_t msr; |
| 513 | int num_threads; |
| 514 | int num_cores; |
| 515 | |
Elyes HAOUAS | a6a396d | 2019-05-26 13:25:30 +0200 | [diff] [blame] | 516 | msr = rdmsr(MSR_CORE_THREAD_COUNT); |
Arthur Heymans | edbf5d9 | 2018-01-25 20:03:42 +0100 | [diff] [blame] | 517 | num_threads = (msr.lo >> 0) & 0xffff; |
| 518 | num_cores = (msr.lo >> 16) & 0xffff; |
| 519 | printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n", |
| 520 | num_cores, num_threads); |
| 521 | |
| 522 | return num_threads; |
| 523 | } |
| 524 | |
| 525 | static void get_microcode_info(const void **microcode, int *parallel) |
| 526 | { |
| 527 | microcode_patch = intel_microcode_find(); |
| 528 | *microcode = microcode_patch; |
| 529 | *parallel = 1; |
| 530 | } |
| 531 | |
| 532 | static void per_cpu_smm_trigger(void) |
| 533 | { |
| 534 | /* Relocate the SMM handler. */ |
| 535 | smm_relocate(); |
| 536 | |
| 537 | /* After SMM relocation a 2nd microcode load is required. */ |
| 538 | intel_microcode_load_unlocked(microcode_patch); |
| 539 | } |
| 540 | |
| 541 | static void post_mp_init(void) |
| 542 | { |
| 543 | /* Now that all APs have been relocated as well as the BSP let SMIs |
| 544 | * start flowing. */ |
| 545 | southbridge_smm_init(); |
| 546 | |
| 547 | /* Lock down the SMRAM space. */ |
| 548 | smm_lock(); |
| 549 | } |
| 550 | |
| 551 | |
| 552 | static const struct mp_ops mp_ops = { |
| 553 | .pre_mp_init = pre_mp_init, |
| 554 | .get_cpu_count = get_cpu_count, |
| 555 | .get_smm_info = smm_info, |
| 556 | .get_microcode_info = get_microcode_info, |
| 557 | .pre_mp_smm_init = smm_initialize, |
| 558 | .per_cpu_smm_trigger = per_cpu_smm_trigger, |
| 559 | .relocation_handler = smm_relocation_handler, |
| 560 | .post_mp_init = post_mp_init, |
| 561 | }; |
| 562 | |
Kyösti Mälkki | b3267e0 | 2019-08-13 16:44:04 +0300 | [diff] [blame] | 563 | void mp_init_cpus(struct bus *cpu_bus) |
Arthur Heymans | edbf5d9 | 2018-01-25 20:03:42 +0100 | [diff] [blame] | 564 | { |
| 565 | if (mp_init_with_smm(cpu_bus, &mp_ops)) |
| 566 | printk(BIOS_ERR, "MP initialization failure.\n"); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 567 | } |
| 568 | |
| 569 | static struct device_operations cpu_dev_ops = { |
| 570 | .init = model_206ax_init, |
| 571 | }; |
| 572 | |
Jonathan Neuschäfer | 8f06ce3 | 2017-11-20 01:56:44 +0100 | [diff] [blame] | 573 | static const struct cpu_device_id cpu_table[] = { |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 574 | { X86_VENDOR_INTEL, 0x206a0 }, /* Intel Sandybridge */ |
| 575 | { X86_VENDOR_INTEL, 0x206a6 }, /* Intel Sandybridge D1 */ |
| 576 | { X86_VENDOR_INTEL, 0x206a7 }, /* Intel Sandybridge D2/J1 */ |
Stefan Reinauer | 08067ba | 2012-10-15 13:47:04 -0700 | [diff] [blame] | 577 | { X86_VENDOR_INTEL, 0x306a0 }, /* Intel IvyBridge */ |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 578 | { X86_VENDOR_INTEL, 0x306a2 }, /* Intel IvyBridge */ |
| 579 | { X86_VENDOR_INTEL, 0x306a4 }, /* Intel IvyBridge */ |
| 580 | { X86_VENDOR_INTEL, 0x306a5 }, /* Intel IvyBridge */ |
| 581 | { X86_VENDOR_INTEL, 0x306a6 }, /* Intel IvyBridge */ |
| 582 | { X86_VENDOR_INTEL, 0x306a8 }, /* Intel IvyBridge */ |
| 583 | { X86_VENDOR_INTEL, 0x306a9 }, /* Intel IvyBridge */ |
| 584 | { 0, 0 }, |
| 585 | }; |
| 586 | |
| 587 | static const struct cpu_driver driver __cpu_driver = { |
| 588 | .ops = &cpu_dev_ops, |
| 589 | .id_table = cpu_table, |
| 590 | .cstates = cstate_map, |
| 591 | }; |