Create i945-ivy smm tseg init based on ivy code.
CPU-side logic is unchanged for this range of CPUs as long as all of them
use TSEG (or ASEG, just needs to be consistent). So uplift 206ax code while
extracting southbridge and APIC code into separate functions.
Change-Id: Ib365681d1da8115922c557fddcc59afc156826da
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10465
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index 74ad0e8..2028af0 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -35,6 +35,9 @@
#include <pc80/mc146818rtc.h>
#include "model_206ax.h"
#include "chip.h"
+#include <cpu/intel/smm/gen1/smi.h>
+
+#define CORE_THREAD_COUNT_MSR 0x35
/*
* List of supported C-states in this processor
@@ -473,6 +476,20 @@
wrmsr(IA32_MC0_STATUS + (i * 4), msr);
}
+int cpu_get_apic_id_map(int *apic_id_map)
+{
+ msr_t msr;
+ int num_cpus, i;
+
+ msr = rdmsr(CORE_THREAD_COUNT_MSR);
+ num_cpus = msr.lo & 0xffff;
+
+ for (i = 0; i < num_cpus && i < CONFIG_MAX_CPUS; i++)
+ apic_id_map[i] = i;
+
+ return num_cpus;
+}
+
/*
* Initialize any extra cores/threads in this package.
*/