Angel Pons | f23ae0b | 2020-04-02 23:48:12 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <device/device.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 5 | #include <acpi/acpi.h> |
Subrata Banik | 53b08c3 | 2018-12-10 14:11:35 +0530 | [diff] [blame] | 6 | #include <arch/cpu.h> |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 7 | #include <cpu/cpu.h> |
| 8 | #include <cpu/x86/mtrr.h> |
| 9 | #include <cpu/x86/msr.h> |
| 10 | #include <cpu/x86/lapic.h> |
Arthur Heymans | edbf5d9 | 2018-01-25 20:03:42 +0100 | [diff] [blame] | 11 | #include <cpu/x86/mp.h> |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 12 | #include <cpu/intel/microcode.h> |
| 13 | #include <cpu/intel/speedstep.h> |
| 14 | #include <cpu/intel/turbo.h> |
| 15 | #include <cpu/x86/cache.h> |
| 16 | #include <cpu/x86/name.h> |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 17 | #include "model_206ax.h" |
Duncan Laurie | 5563211 | 2012-07-16 12:19:00 -0700 | [diff] [blame] | 18 | #include "chip.h" |
Kyösti Mälkki | f091f4d | 2019-08-14 03:49:21 +0300 | [diff] [blame] | 19 | #include <cpu/intel/smm_reloc.h> |
Matt DeVillier | ed6fe2f | 2016-12-14 16:12:43 -0600 | [diff] [blame] | 20 | #include <cpu/intel/common/common.h> |
Michał Żygowski | 0d11dbf | 2020-10-31 21:43:25 +0100 | [diff] [blame^] | 21 | #include <smbios.h> |
Vladimir Serbinenko | c16e9dfa | 2015-05-29 16:18:01 +0200 | [diff] [blame] | 22 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 23 | /* |
Martin Roth | 4c3ab73 | 2013-07-08 16:23:54 -0600 | [diff] [blame] | 24 | * List of supported C-states in this processor |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 25 | * |
| 26 | * Latencies are typical worst-case package exit time in uS |
| 27 | * taken from the SandyBridge BIOS specification. |
| 28 | */ |
| 29 | static acpi_cstate_t cstate_map[] = { |
| 30 | { /* 0: C0 */ |
Lee Leahy | 9d62e7e | 2017-03-15 17:40:50 -0700 | [diff] [blame] | 31 | }, { /* 1: C1 */ |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 32 | .latency = 1, |
| 33 | .power = 1000, |
| 34 | .resource = { |
| 35 | .addrl = 0x00, /* MWAIT State 0 */ |
| 36 | .space_id = ACPI_ADDRESS_SPACE_FIXED, |
| 37 | .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, |
| 38 | .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, |
Elyes HAOUAS | 8ee161d | 2019-03-03 12:49:56 +0100 | [diff] [blame] | 39 | .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 40 | } |
| 41 | }, |
| 42 | { /* 2: C1E */ |
| 43 | .latency = 1, |
| 44 | .power = 1000, |
| 45 | .resource = { |
| 46 | .addrl = 0x01, /* MWAIT State 0 Sub-state 1 */ |
| 47 | .space_id = ACPI_ADDRESS_SPACE_FIXED, |
| 48 | .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, |
| 49 | .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, |
Elyes HAOUAS | 8ee161d | 2019-03-03 12:49:56 +0100 | [diff] [blame] | 50 | .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 51 | } |
| 52 | }, |
| 53 | { /* 3: C3 */ |
| 54 | .latency = 63, |
| 55 | .power = 500, |
| 56 | .resource = { |
| 57 | .addrl = 0x10, /* MWAIT State 1 */ |
| 58 | .space_id = ACPI_ADDRESS_SPACE_FIXED, |
| 59 | .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, |
| 60 | .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, |
Elyes HAOUAS | 8ee161d | 2019-03-03 12:49:56 +0100 | [diff] [blame] | 61 | .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 62 | } |
| 63 | }, |
| 64 | { /* 4: C6 */ |
| 65 | .latency = 87, |
| 66 | .power = 350, |
| 67 | .resource = { |
| 68 | .addrl = 0x20, /* MWAIT State 2 */ |
| 69 | .space_id = ACPI_ADDRESS_SPACE_FIXED, |
| 70 | .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, |
| 71 | .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, |
Elyes HAOUAS | 8ee161d | 2019-03-03 12:49:56 +0100 | [diff] [blame] | 72 | .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 73 | } |
| 74 | }, |
| 75 | { /* 5: C7 */ |
| 76 | .latency = 90, |
| 77 | .power = 200, |
| 78 | .resource = { |
| 79 | .addrl = 0x30, /* MWAIT State 3 */ |
| 80 | .space_id = ACPI_ADDRESS_SPACE_FIXED, |
| 81 | .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, |
| 82 | .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, |
Elyes HAOUAS | 8ee161d | 2019-03-03 12:49:56 +0100 | [diff] [blame] | 83 | .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 84 | } |
| 85 | }, |
| 86 | { /* 6: C7S */ |
| 87 | .latency = 90, |
| 88 | .power = 200, |
| 89 | .resource = { |
| 90 | .addrl = 0x31, /* MWAIT State 3 Sub-state 1 */ |
| 91 | .space_id = ACPI_ADDRESS_SPACE_FIXED, |
| 92 | .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, |
| 93 | .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, |
Elyes HAOUAS | 8ee161d | 2019-03-03 12:49:56 +0100 | [diff] [blame] | 94 | .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 95 | } |
| 96 | }, |
| 97 | { 0 } |
| 98 | }; |
| 99 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 100 | /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ |
| 101 | static const u8 power_limit_time_sec_to_msr[] = { |
| 102 | [0] = 0x00, |
| 103 | [1] = 0x0a, |
| 104 | [2] = 0x0b, |
| 105 | [3] = 0x4b, |
| 106 | [4] = 0x0c, |
| 107 | [5] = 0x2c, |
| 108 | [6] = 0x4c, |
| 109 | [7] = 0x6c, |
| 110 | [8] = 0x0d, |
| 111 | [10] = 0x2d, |
| 112 | [12] = 0x4d, |
| 113 | [14] = 0x6d, |
| 114 | [16] = 0x0e, |
| 115 | [20] = 0x2e, |
| 116 | [24] = 0x4e, |
| 117 | [28] = 0x6e, |
| 118 | [32] = 0x0f, |
| 119 | [40] = 0x2f, |
| 120 | [48] = 0x4f, |
| 121 | [56] = 0x6f, |
| 122 | [64] = 0x10, |
| 123 | [80] = 0x30, |
| 124 | [96] = 0x50, |
| 125 | [112] = 0x70, |
| 126 | [128] = 0x11, |
| 127 | }; |
| 128 | |
| 129 | /* Convert POWER_LIMIT_1_TIME MSR value to seconds */ |
| 130 | static const u8 power_limit_time_msr_to_sec[] = { |
| 131 | [0x00] = 0, |
| 132 | [0x0a] = 1, |
| 133 | [0x0b] = 2, |
| 134 | [0x4b] = 3, |
| 135 | [0x0c] = 4, |
| 136 | [0x2c] = 5, |
| 137 | [0x4c] = 6, |
| 138 | [0x6c] = 7, |
| 139 | [0x0d] = 8, |
| 140 | [0x2d] = 10, |
| 141 | [0x4d] = 12, |
| 142 | [0x6d] = 14, |
| 143 | [0x0e] = 16, |
| 144 | [0x2e] = 20, |
| 145 | [0x4e] = 24, |
| 146 | [0x6e] = 28, |
| 147 | [0x0f] = 32, |
| 148 | [0x2f] = 40, |
| 149 | [0x4f] = 48, |
| 150 | [0x6f] = 56, |
| 151 | [0x10] = 64, |
| 152 | [0x30] = 80, |
| 153 | [0x50] = 96, |
| 154 | [0x70] = 112, |
| 155 | [0x11] = 128, |
| 156 | }; |
| 157 | |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 158 | int cpu_config_tdp_levels(void) |
| 159 | { |
| 160 | msr_t platform_info; |
| 161 | |
| 162 | /* Minimum CPU revision */ |
| 163 | if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID) |
| 164 | return 0; |
| 165 | |
| 166 | /* Bits 34:33 indicate how many levels supported */ |
| 167 | platform_info = rdmsr(MSR_PLATFORM_INFO); |
| 168 | return (platform_info.hi >> 1) & 3; |
| 169 | } |
| 170 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 171 | /* |
| 172 | * Configure processor power limits if possible |
| 173 | * This must be done AFTER set of BIOS_RESET_CPL |
| 174 | */ |
| 175 | void set_power_limits(u8 power_limit_1_time) |
| 176 | { |
| 177 | msr_t msr = rdmsr(MSR_PLATFORM_INFO); |
| 178 | msr_t limit; |
Lee Leahy | 73a2894 | 2017-03-15 17:52:06 -0700 | [diff] [blame] | 179 | unsigned int power_unit; |
| 180 | unsigned int tdp, min_power, max_power, max_time; |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 181 | u8 power_limit_1_val; |
| 182 | |
Edward O'Callaghan | 5cfef13 | 2014-08-03 20:00:47 +1000 | [diff] [blame] | 183 | if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 184 | return; |
| 185 | |
| 186 | if (!(msr.lo & PLATFORM_INFO_SET_TDP)) |
| 187 | return; |
| 188 | |
| 189 | /* Get units */ |
| 190 | msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); |
| 191 | power_unit = 2 << ((msr.lo & 0xf) - 1); |
| 192 | |
| 193 | /* Get power defaults for this SKU */ |
| 194 | msr = rdmsr(MSR_PKG_POWER_SKU); |
| 195 | tdp = msr.lo & 0x7fff; |
| 196 | min_power = (msr.lo >> 16) & 0x7fff; |
| 197 | max_power = msr.hi & 0x7fff; |
| 198 | max_time = (msr.hi >> 16) & 0x7f; |
| 199 | |
| 200 | printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit); |
| 201 | |
| 202 | if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time) |
| 203 | power_limit_1_time = power_limit_time_msr_to_sec[max_time]; |
| 204 | |
| 205 | if (min_power > 0 && tdp < min_power) |
| 206 | tdp = min_power; |
| 207 | |
| 208 | if (max_power > 0 && tdp > max_power) |
| 209 | tdp = max_power; |
| 210 | |
| 211 | power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time]; |
| 212 | |
| 213 | /* Set long term power limit to TDP */ |
| 214 | limit.lo = 0; |
| 215 | limit.lo |= tdp & PKG_POWER_LIMIT_MASK; |
| 216 | limit.lo |= PKG_POWER_LIMIT_EN; |
| 217 | limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << |
| 218 | PKG_POWER_LIMIT_TIME_SHIFT; |
| 219 | |
| 220 | /* Set short term power limit to 1.25 * TDP */ |
| 221 | limit.hi = 0; |
| 222 | limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK; |
| 223 | limit.hi |= PKG_POWER_LIMIT_EN; |
| 224 | /* Power limit 2 time is only programmable on SNB EP/EX */ |
| 225 | |
| 226 | wrmsr(MSR_PKG_POWER_LIMIT, limit); |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 227 | |
| 228 | /* Use nominal TDP values for CPUs with configurable TDP */ |
| 229 | if (cpu_config_tdp_levels()) { |
| 230 | msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); |
| 231 | limit.hi = 0; |
| 232 | limit.lo = msr.lo & 0xff; |
| 233 | wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit); |
| 234 | } |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 235 | } |
| 236 | |
| 237 | static void configure_c_states(void) |
| 238 | { |
| 239 | msr_t msr; |
| 240 | |
Elyes HAOUAS | 4e6b790 | 2018-10-02 08:44:47 +0200 | [diff] [blame] | 241 | msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 242 | msr.lo |= (1 << 28); // C1 Auto Undemotion Enable |
| 243 | msr.lo |= (1 << 27); // C3 Auto Undemotion Enable |
| 244 | msr.lo |= (1 << 26); // C1 Auto Demotion Enable |
| 245 | msr.lo |= (1 << 25); // C3 Auto Demotion Enable |
| 246 | msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection |
| 247 | msr.lo |= 7; // No package C-state limit |
Patrick Rudolph | 573481b | 2020-03-02 14:21:32 +0100 | [diff] [blame] | 248 | |
| 249 | msr.lo |= (1 << 15); // Lock C-State MSR |
Elyes HAOUAS | 4e6b790 | 2018-10-02 08:44:47 +0200 | [diff] [blame] | 250 | wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 251 | |
Patrick Georgi | 644e83b | 2013-02-09 15:35:30 +0100 | [diff] [blame] | 252 | msr = rdmsr(MSR_PMG_IO_CAPTURE_ADDR); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 253 | msr.lo &= ~0x7ffff; |
| 254 | msr.lo |= (PMB0_BASE + 4); // LVL_2 base address |
| 255 | msr.lo |= (2 << 16); // CST Range: C7 is max C-state |
Patrick Georgi | 644e83b | 2013-02-09 15:35:30 +0100 | [diff] [blame] | 256 | wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 257 | |
| 258 | msr = rdmsr(MSR_MISC_PWR_MGMT); |
| 259 | msr.lo &= ~(1 << 0); // Enable P-state HW_ALL coordination |
| 260 | wrmsr(MSR_MISC_PWR_MGMT, msr); |
| 261 | |
| 262 | msr = rdmsr(MSR_POWER_CTL); |
| 263 | msr.lo |= (1 << 18); // Enable Energy Perf Bias MSR 0x1b0 |
| 264 | msr.lo |= (1 << 1); // C1E Enable |
| 265 | msr.lo |= (1 << 0); // Bi-directional PROCHOT# |
| 266 | wrmsr(MSR_POWER_CTL, msr); |
| 267 | |
| 268 | /* C3 Interrupt Response Time Limit */ |
| 269 | msr.hi = 0; |
| 270 | msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50; |
| 271 | wrmsr(MSR_PKGC3_IRTL, msr); |
| 272 | |
| 273 | /* C6 Interrupt Response Time Limit */ |
| 274 | msr.hi = 0; |
| 275 | msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68; |
| 276 | wrmsr(MSR_PKGC6_IRTL, msr); |
| 277 | |
| 278 | /* C7 Interrupt Response Time Limit */ |
| 279 | msr.hi = 0; |
| 280 | msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D; |
| 281 | wrmsr(MSR_PKGC7_IRTL, msr); |
| 282 | |
| 283 | /* Primary Plane Current Limit */ |
| 284 | msr = rdmsr(MSR_PP0_CURRENT_CONFIG); |
| 285 | msr.lo &= ~0x1fff; |
| 286 | msr.lo |= PP0_CURRENT_LIMIT; |
| 287 | wrmsr(MSR_PP0_CURRENT_CONFIG, msr); |
| 288 | |
| 289 | /* Secondary Plane Current Limit */ |
| 290 | msr = rdmsr(MSR_PP1_CURRENT_CONFIG); |
| 291 | msr.lo &= ~0x1fff; |
Duncan Laurie | 4e4320f | 2012-06-25 09:53:58 -0700 | [diff] [blame] | 292 | if (cpuid_eax(1) >= 0x30600) |
| 293 | msr.lo |= PP1_CURRENT_LIMIT_IVB; |
| 294 | else |
| 295 | msr.lo |= PP1_CURRENT_LIMIT_SNB; |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 296 | wrmsr(MSR_PP1_CURRENT_CONFIG, msr); |
| 297 | } |
| 298 | |
Duncan Laurie | 5563211 | 2012-07-16 12:19:00 -0700 | [diff] [blame] | 299 | static void configure_thermal_target(void) |
| 300 | { |
| 301 | struct cpu_intel_model_206ax_config *conf; |
Edward O'Callaghan | 2c9d2cf | 2014-10-27 23:29:29 +1100 | [diff] [blame] | 302 | struct device *lapic; |
Duncan Laurie | 5563211 | 2012-07-16 12:19:00 -0700 | [diff] [blame] | 303 | msr_t msr; |
| 304 | |
| 305 | /* Find pointer to CPU configuration */ |
| 306 | lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); |
| 307 | if (!lapic || !lapic->chip_info) |
| 308 | return; |
| 309 | conf = lapic->chip_info; |
| 310 | |
Martin Roth | 4c3ab73 | 2013-07-08 16:23:54 -0600 | [diff] [blame] | 311 | /* Set TCC activation offset if supported */ |
Duncan Laurie | 5563211 | 2012-07-16 12:19:00 -0700 | [diff] [blame] | 312 | msr = rdmsr(MSR_PLATFORM_INFO); |
| 313 | if ((msr.lo & (1 << 30)) && conf->tcc_offset) { |
| 314 | msr = rdmsr(MSR_TEMPERATURE_TARGET); |
| 315 | msr.lo &= ~(0xf << 24); /* Bits 27:24 */ |
| 316 | msr.lo |= (conf->tcc_offset & 0xf) << 24; |
| 317 | wrmsr(MSR_TEMPERATURE_TARGET, msr); |
| 318 | } |
| 319 | } |
| 320 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 321 | static void configure_misc(void) |
| 322 | { |
| 323 | msr_t msr; |
| 324 | |
| 325 | msr = rdmsr(IA32_MISC_ENABLE); |
| 326 | msr.lo |= (1 << 0); /* Fast String enable */ |
Lee Leahy | 7b5f12b9 | 2017-03-15 17:16:59 -0700 | [diff] [blame] | 327 | msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 328 | msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ |
| 329 | wrmsr(IA32_MISC_ENABLE, msr); |
| 330 | |
| 331 | /* Disable Thermal interrupts */ |
| 332 | msr.lo = 0; |
| 333 | msr.hi = 0; |
| 334 | wrmsr(IA32_THERM_INTERRUPT, msr); |
| 335 | |
| 336 | /* Enable package critical interrupt only */ |
| 337 | msr.lo = 1 << 4; |
| 338 | msr.hi = 0; |
| 339 | wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); |
| 340 | } |
| 341 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 342 | static void set_max_ratio(void) |
| 343 | { |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 344 | msr_t msr, perf_ctl; |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 345 | |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 346 | perf_ctl.hi = 0; |
| 347 | |
| 348 | /* Check for configurable TDP option */ |
| 349 | if (cpu_config_tdp_levels()) { |
| 350 | /* Set to nominal TDP ratio */ |
| 351 | msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); |
| 352 | perf_ctl.lo = (msr.lo & 0xff) << 8; |
| 353 | } else { |
| 354 | /* Platform Info bits 15:8 give max ratio */ |
| 355 | msr = rdmsr(MSR_PLATFORM_INFO); |
| 356 | perf_ctl.lo = msr.lo & 0xff00; |
| 357 | } |
| 358 | wrmsr(IA32_PERF_CTL, perf_ctl); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 359 | |
| 360 | printk(BIOS_DEBUG, "model_x06ax: frequency set to %d\n", |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 361 | ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 362 | } |
| 363 | |
Michał Żygowski | 0d11dbf | 2020-10-31 21:43:25 +0100 | [diff] [blame^] | 364 | unsigned int smbios_cpu_get_max_speed_mhz(void) |
| 365 | { |
| 366 | msr_t msr; |
| 367 | msr = rdmsr(MSR_TURBO_RATIO_LIMIT); |
| 368 | return (msr.lo & 0xff) * SANDYBRIDGE_BCLK; |
| 369 | } |
| 370 | |
| 371 | unsigned int smbios_cpu_get_current_speed_mhz(void) |
| 372 | { |
| 373 | msr_t msr; |
| 374 | msr = rdmsr(MSR_PLATFORM_INFO); |
| 375 | return ((msr.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK; |
| 376 | } |
| 377 | |
| 378 | unsigned int smbios_processor_external_clock(void) |
| 379 | { |
| 380 | return SANDYBRIDGE_BCLK; |
| 381 | } |
| 382 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 383 | static void configure_mca(void) |
| 384 | { |
| 385 | msr_t msr; |
| 386 | int i; |
Dan Elkouby | dfaff4d | 2018-09-03 18:34:07 +0300 | [diff] [blame] | 387 | int num_banks; |
| 388 | |
| 389 | msr = rdmsr(IA32_MCG_CAP); |
| 390 | num_banks = msr.lo & 0xff; |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 391 | |
| 392 | msr.lo = msr.hi = 0; |
| 393 | /* This should only be done on a cold boot */ |
Dan Elkouby | dfaff4d | 2018-09-03 18:34:07 +0300 | [diff] [blame] | 394 | for (i = 0; i < num_banks; i++) |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 395 | wrmsr(IA32_MC0_STATUS + (i * 4), msr); |
| 396 | } |
| 397 | |
Patrick Rudolph | 9e1b9b5 | 2018-07-27 17:25:05 +0200 | [diff] [blame] | 398 | static void model_206ax_report(void) |
| 399 | { |
| 400 | static const char *const mode[] = {"NOT ", ""}; |
Patrick Rudolph | 9e1b9b5 | 2018-07-27 17:25:05 +0200 | [diff] [blame] | 401 | char processor_name[49]; |
| 402 | int vt, txt, aes; |
Subrata Banik | 53b08c3 | 2018-12-10 14:11:35 +0530 | [diff] [blame] | 403 | uint32_t cpu_id, cpu_feature_flag; |
Patrick Rudolph | 9e1b9b5 | 2018-07-27 17:25:05 +0200 | [diff] [blame] | 404 | |
| 405 | /* Print processor name */ |
| 406 | fill_processor_name(processor_name); |
| 407 | printk(BIOS_INFO, "CPU: %s.\n", processor_name); |
| 408 | |
| 409 | /* Print platform ID */ |
| 410 | printk(BIOS_INFO, "CPU: platform id %x\n", get_platform_id()); |
| 411 | |
| 412 | /* CPUID and features */ |
Subrata Banik | 53b08c3 | 2018-12-10 14:11:35 +0530 | [diff] [blame] | 413 | cpu_id = cpu_get_cpuid(); |
| 414 | printk(BIOS_INFO, "CPU: cpuid(1) 0x%x\n", cpu_id); |
| 415 | |
| 416 | cpu_feature_flag = cpu_get_feature_flags_ecx(); |
| 417 | aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0; |
| 418 | txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0; |
| 419 | vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0; |
Patrick Rudolph | 9e1b9b5 | 2018-07-27 17:25:05 +0200 | [diff] [blame] | 420 | printk(BIOS_INFO, "CPU: AES %ssupported\n", mode[aes]); |
| 421 | printk(BIOS_INFO, "CPU: TXT %ssupported\n", mode[txt]); |
| 422 | printk(BIOS_INFO, "CPU: VT %ssupported\n", mode[vt]); |
| 423 | } |
| 424 | |
Edward O'Callaghan | 2c9d2cf | 2014-10-27 23:29:29 +1100 | [diff] [blame] | 425 | static void model_206ax_init(struct device *cpu) |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 426 | { |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 427 | |
| 428 | /* Turn on caching if we haven't already */ |
| 429 | x86_enable_cache(); |
| 430 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 431 | /* Clear out pending MCEs */ |
| 432 | configure_mca(); |
| 433 | |
Patrick Rudolph | 9e1b9b5 | 2018-07-27 17:25:05 +0200 | [diff] [blame] | 434 | /* Print infos */ |
| 435 | model_206ax_report(); |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 436 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 437 | /* Setup Page Attribute Tables (PAT) */ |
| 438 | // TODO set up PAT |
| 439 | |
Elyes HAOUAS | d6e9686 | 2016-08-21 10:12:15 +0200 | [diff] [blame] | 440 | /* Enable the local CPU APICs */ |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 441 | enable_lapic_tpr(); |
| 442 | setup_lapic(); |
| 443 | |
Matt DeVillier | ed6fe2f | 2016-12-14 16:12:43 -0600 | [diff] [blame] | 444 | /* Set virtualization based on Kconfig option */ |
Matt DeVillier | f9aed65 | 2018-12-15 15:57:33 -0600 | [diff] [blame] | 445 | set_vmx_and_lock(); |
Marc Jones | 5986eda | 2012-10-25 09:37:19 -0600 | [diff] [blame] | 446 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 447 | /* Configure C States */ |
| 448 | configure_c_states(); |
| 449 | |
| 450 | /* Configure Enhanced SpeedStep and Thermal Sensors */ |
| 451 | configure_misc(); |
| 452 | |
Duncan Laurie | 5563211 | 2012-07-16 12:19:00 -0700 | [diff] [blame] | 453 | /* Thermal throttle activation offset */ |
| 454 | configure_thermal_target(); |
| 455 | |
Michael Niewöhner | 6303243 | 2020-10-11 17:34:54 +0200 | [diff] [blame] | 456 | set_aesni_lock(); |
Michael Niewöhner | 7f8767d | 2020-10-18 00:45:38 +0200 | [diff] [blame] | 457 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 458 | /* Enable Direct Cache Access */ |
| 459 | configure_dca_cap(); |
| 460 | |
| 461 | /* Set energy policy */ |
| 462 | set_energy_perf_bias(ENERGY_POLICY_NORMAL); |
| 463 | |
| 464 | /* Set Max Ratio */ |
| 465 | set_max_ratio(); |
| 466 | |
| 467 | /* Enable Turbo */ |
| 468 | enable_turbo(); |
Arthur Heymans | edbf5d9 | 2018-01-25 20:03:42 +0100 | [diff] [blame] | 469 | } |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 470 | |
Arthur Heymans | edbf5d9 | 2018-01-25 20:03:42 +0100 | [diff] [blame] | 471 | /* MP initialization support. */ |
| 472 | static const void *microcode_patch; |
| 473 | |
| 474 | static void pre_mp_init(void) |
| 475 | { |
| 476 | /* Setup MTRRs based on physical address size. */ |
| 477 | x86_setup_mtrrs_with_detect(); |
| 478 | x86_mtrr_check(); |
| 479 | } |
| 480 | |
| 481 | static int get_cpu_count(void) |
| 482 | { |
| 483 | msr_t msr; |
| 484 | int num_threads; |
| 485 | int num_cores; |
| 486 | |
Elyes HAOUAS | a6a396d | 2019-05-26 13:25:30 +0200 | [diff] [blame] | 487 | msr = rdmsr(MSR_CORE_THREAD_COUNT); |
Arthur Heymans | edbf5d9 | 2018-01-25 20:03:42 +0100 | [diff] [blame] | 488 | num_threads = (msr.lo >> 0) & 0xffff; |
| 489 | num_cores = (msr.lo >> 16) & 0xffff; |
| 490 | printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n", |
| 491 | num_cores, num_threads); |
| 492 | |
| 493 | return num_threads; |
| 494 | } |
| 495 | |
| 496 | static void get_microcode_info(const void **microcode, int *parallel) |
| 497 | { |
| 498 | microcode_patch = intel_microcode_find(); |
| 499 | *microcode = microcode_patch; |
| 500 | *parallel = 1; |
| 501 | } |
| 502 | |
| 503 | static void per_cpu_smm_trigger(void) |
| 504 | { |
| 505 | /* Relocate the SMM handler. */ |
| 506 | smm_relocate(); |
| 507 | |
| 508 | /* After SMM relocation a 2nd microcode load is required. */ |
| 509 | intel_microcode_load_unlocked(microcode_patch); |
| 510 | } |
| 511 | |
| 512 | static void post_mp_init(void) |
| 513 | { |
| 514 | /* Now that all APs have been relocated as well as the BSP let SMIs |
| 515 | * start flowing. */ |
Kyösti Mälkki | 0778c86 | 2020-06-10 12:44:03 +0300 | [diff] [blame] | 516 | global_smi_enable(); |
Arthur Heymans | edbf5d9 | 2018-01-25 20:03:42 +0100 | [diff] [blame] | 517 | |
| 518 | /* Lock down the SMRAM space. */ |
| 519 | smm_lock(); |
| 520 | } |
| 521 | |
Arthur Heymans | edbf5d9 | 2018-01-25 20:03:42 +0100 | [diff] [blame] | 522 | static const struct mp_ops mp_ops = { |
| 523 | .pre_mp_init = pre_mp_init, |
| 524 | .get_cpu_count = get_cpu_count, |
| 525 | .get_smm_info = smm_info, |
| 526 | .get_microcode_info = get_microcode_info, |
| 527 | .pre_mp_smm_init = smm_initialize, |
| 528 | .per_cpu_smm_trigger = per_cpu_smm_trigger, |
| 529 | .relocation_handler = smm_relocation_handler, |
| 530 | .post_mp_init = post_mp_init, |
| 531 | }; |
| 532 | |
Kyösti Mälkki | b3267e0 | 2019-08-13 16:44:04 +0300 | [diff] [blame] | 533 | void mp_init_cpus(struct bus *cpu_bus) |
Arthur Heymans | edbf5d9 | 2018-01-25 20:03:42 +0100 | [diff] [blame] | 534 | { |
| 535 | if (mp_init_with_smm(cpu_bus, &mp_ops)) |
| 536 | printk(BIOS_ERR, "MP initialization failure.\n"); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 537 | } |
| 538 | |
| 539 | static struct device_operations cpu_dev_ops = { |
| 540 | .init = model_206ax_init, |
| 541 | }; |
| 542 | |
Jonathan Neuschäfer | 8f06ce3 | 2017-11-20 01:56:44 +0100 | [diff] [blame] | 543 | static const struct cpu_device_id cpu_table[] = { |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 544 | { X86_VENDOR_INTEL, 0x206a0 }, /* Intel Sandybridge */ |
| 545 | { X86_VENDOR_INTEL, 0x206a6 }, /* Intel Sandybridge D1 */ |
| 546 | { X86_VENDOR_INTEL, 0x206a7 }, /* Intel Sandybridge D2/J1 */ |
Stefan Reinauer | 08067ba | 2012-10-15 13:47:04 -0700 | [diff] [blame] | 547 | { X86_VENDOR_INTEL, 0x306a0 }, /* Intel IvyBridge */ |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 548 | { X86_VENDOR_INTEL, 0x306a2 }, /* Intel IvyBridge */ |
| 549 | { X86_VENDOR_INTEL, 0x306a4 }, /* Intel IvyBridge */ |
| 550 | { X86_VENDOR_INTEL, 0x306a5 }, /* Intel IvyBridge */ |
| 551 | { X86_VENDOR_INTEL, 0x306a6 }, /* Intel IvyBridge */ |
| 552 | { X86_VENDOR_INTEL, 0x306a8 }, /* Intel IvyBridge */ |
| 553 | { X86_VENDOR_INTEL, 0x306a9 }, /* Intel IvyBridge */ |
| 554 | { 0, 0 }, |
| 555 | }; |
| 556 | |
| 557 | static const struct cpu_driver driver __cpu_driver = { |
| 558 | .ops = &cpu_dev_ops, |
| 559 | .id_table = cpu_table, |
| 560 | .cstates = cstate_map, |
| 561 | }; |