Angel Pons | f23ae0b | 2020-04-02 23:48:12 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <device/device.h> |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 5 | #include <cpu/cpu.h> |
| 6 | #include <cpu/x86/mtrr.h> |
| 7 | #include <cpu/x86/msr.h> |
Arthur Heymans | edbf5d9 | 2018-01-25 20:03:42 +0100 | [diff] [blame] | 8 | #include <cpu/x86/mp.h> |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 9 | #include <cpu/intel/microcode.h> |
| 10 | #include <cpu/intel/speedstep.h> |
| 11 | #include <cpu/intel/turbo.h> |
| 12 | #include <cpu/x86/cache.h> |
| 13 | #include <cpu/x86/name.h> |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 14 | #include "model_206ax.h" |
Duncan Laurie | 5563211 | 2012-07-16 12:19:00 -0700 | [diff] [blame] | 15 | #include "chip.h" |
Kyösti Mälkki | f091f4d | 2019-08-14 03:49:21 +0300 | [diff] [blame] | 16 | #include <cpu/intel/smm_reloc.h> |
Matt DeVillier | ed6fe2f | 2016-12-14 16:12:43 -0600 | [diff] [blame] | 17 | #include <cpu/intel/common/common.h> |
Michał Żygowski | 0d11dbf | 2020-10-31 21:43:25 +0100 | [diff] [blame] | 18 | #include <smbios.h> |
Felix Held | d27ef5b | 2021-10-20 20:18:12 +0200 | [diff] [blame] | 19 | #include <types.h> |
Vladimir Serbinenko | c16e9dfa | 2015-05-29 16:18:01 +0200 | [diff] [blame] | 20 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 21 | /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ |
| 22 | static const u8 power_limit_time_sec_to_msr[] = { |
| 23 | [0] = 0x00, |
| 24 | [1] = 0x0a, |
| 25 | [2] = 0x0b, |
| 26 | [3] = 0x4b, |
| 27 | [4] = 0x0c, |
| 28 | [5] = 0x2c, |
| 29 | [6] = 0x4c, |
| 30 | [7] = 0x6c, |
| 31 | [8] = 0x0d, |
| 32 | [10] = 0x2d, |
| 33 | [12] = 0x4d, |
| 34 | [14] = 0x6d, |
| 35 | [16] = 0x0e, |
| 36 | [20] = 0x2e, |
| 37 | [24] = 0x4e, |
| 38 | [28] = 0x6e, |
| 39 | [32] = 0x0f, |
| 40 | [40] = 0x2f, |
| 41 | [48] = 0x4f, |
| 42 | [56] = 0x6f, |
| 43 | [64] = 0x10, |
| 44 | [80] = 0x30, |
| 45 | [96] = 0x50, |
| 46 | [112] = 0x70, |
| 47 | [128] = 0x11, |
| 48 | }; |
| 49 | |
| 50 | /* Convert POWER_LIMIT_1_TIME MSR value to seconds */ |
| 51 | static const u8 power_limit_time_msr_to_sec[] = { |
| 52 | [0x00] = 0, |
| 53 | [0x0a] = 1, |
| 54 | [0x0b] = 2, |
| 55 | [0x4b] = 3, |
| 56 | [0x0c] = 4, |
| 57 | [0x2c] = 5, |
| 58 | [0x4c] = 6, |
| 59 | [0x6c] = 7, |
| 60 | [0x0d] = 8, |
| 61 | [0x2d] = 10, |
| 62 | [0x4d] = 12, |
| 63 | [0x6d] = 14, |
| 64 | [0x0e] = 16, |
| 65 | [0x2e] = 20, |
| 66 | [0x4e] = 24, |
| 67 | [0x6e] = 28, |
| 68 | [0x0f] = 32, |
| 69 | [0x2f] = 40, |
| 70 | [0x4f] = 48, |
| 71 | [0x6f] = 56, |
| 72 | [0x10] = 64, |
| 73 | [0x30] = 80, |
| 74 | [0x50] = 96, |
| 75 | [0x70] = 112, |
| 76 | [0x11] = 128, |
| 77 | }; |
| 78 | |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 79 | int cpu_config_tdp_levels(void) |
| 80 | { |
| 81 | msr_t platform_info; |
| 82 | |
| 83 | /* Minimum CPU revision */ |
| 84 | if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID) |
| 85 | return 0; |
| 86 | |
| 87 | /* Bits 34:33 indicate how many levels supported */ |
| 88 | platform_info = rdmsr(MSR_PLATFORM_INFO); |
| 89 | return (platform_info.hi >> 1) & 3; |
| 90 | } |
| 91 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 92 | /* |
| 93 | * Configure processor power limits if possible |
| 94 | * This must be done AFTER set of BIOS_RESET_CPL |
| 95 | */ |
| 96 | void set_power_limits(u8 power_limit_1_time) |
| 97 | { |
| 98 | msr_t msr = rdmsr(MSR_PLATFORM_INFO); |
| 99 | msr_t limit; |
Lee Leahy | 73a2894 | 2017-03-15 17:52:06 -0700 | [diff] [blame] | 100 | unsigned int power_unit; |
| 101 | unsigned int tdp, min_power, max_power, max_time; |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 102 | u8 power_limit_1_val; |
| 103 | |
Edward O'Callaghan | 5cfef13 | 2014-08-03 20:00:47 +1000 | [diff] [blame] | 104 | if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 105 | return; |
| 106 | |
| 107 | if (!(msr.lo & PLATFORM_INFO_SET_TDP)) |
| 108 | return; |
| 109 | |
| 110 | /* Get units */ |
| 111 | msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); |
| 112 | power_unit = 2 << ((msr.lo & 0xf) - 1); |
| 113 | |
| 114 | /* Get power defaults for this SKU */ |
| 115 | msr = rdmsr(MSR_PKG_POWER_SKU); |
| 116 | tdp = msr.lo & 0x7fff; |
| 117 | min_power = (msr.lo >> 16) & 0x7fff; |
| 118 | max_power = msr.hi & 0x7fff; |
| 119 | max_time = (msr.hi >> 16) & 0x7f; |
| 120 | |
| 121 | printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit); |
| 122 | |
| 123 | if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time) |
| 124 | power_limit_1_time = power_limit_time_msr_to_sec[max_time]; |
| 125 | |
| 126 | if (min_power > 0 && tdp < min_power) |
| 127 | tdp = min_power; |
| 128 | |
| 129 | if (max_power > 0 && tdp > max_power) |
| 130 | tdp = max_power; |
| 131 | |
| 132 | power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time]; |
| 133 | |
| 134 | /* Set long term power limit to TDP */ |
| 135 | limit.lo = 0; |
| 136 | limit.lo |= tdp & PKG_POWER_LIMIT_MASK; |
| 137 | limit.lo |= PKG_POWER_LIMIT_EN; |
| 138 | limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << |
| 139 | PKG_POWER_LIMIT_TIME_SHIFT; |
| 140 | |
| 141 | /* Set short term power limit to 1.25 * TDP */ |
| 142 | limit.hi = 0; |
| 143 | limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK; |
| 144 | limit.hi |= PKG_POWER_LIMIT_EN; |
| 145 | /* Power limit 2 time is only programmable on SNB EP/EX */ |
| 146 | |
| 147 | wrmsr(MSR_PKG_POWER_LIMIT, limit); |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 148 | |
| 149 | /* Use nominal TDP values for CPUs with configurable TDP */ |
| 150 | if (cpu_config_tdp_levels()) { |
| 151 | msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); |
| 152 | limit.hi = 0; |
| 153 | limit.lo = msr.lo & 0xff; |
| 154 | wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit); |
| 155 | } |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 156 | } |
| 157 | |
| 158 | static void configure_c_states(void) |
| 159 | { |
| 160 | msr_t msr; |
| 161 | |
Elyes HAOUAS | 4e6b790 | 2018-10-02 08:44:47 +0200 | [diff] [blame] | 162 | msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 163 | msr.lo |= (1 << 28); // C1 Auto Undemotion Enable |
| 164 | msr.lo |= (1 << 27); // C3 Auto Undemotion Enable |
| 165 | msr.lo |= (1 << 26); // C1 Auto Demotion Enable |
| 166 | msr.lo |= (1 << 25); // C3 Auto Demotion Enable |
| 167 | msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection |
| 168 | msr.lo |= 7; // No package C-state limit |
Patrick Rudolph | 573481b | 2020-03-02 14:21:32 +0100 | [diff] [blame] | 169 | |
| 170 | msr.lo |= (1 << 15); // Lock C-State MSR |
Elyes HAOUAS | 4e6b790 | 2018-10-02 08:44:47 +0200 | [diff] [blame] | 171 | wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 172 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 173 | msr = rdmsr(MSR_MISC_PWR_MGMT); |
| 174 | msr.lo &= ~(1 << 0); // Enable P-state HW_ALL coordination |
| 175 | wrmsr(MSR_MISC_PWR_MGMT, msr); |
| 176 | |
| 177 | msr = rdmsr(MSR_POWER_CTL); |
| 178 | msr.lo |= (1 << 18); // Enable Energy Perf Bias MSR 0x1b0 |
| 179 | msr.lo |= (1 << 1); // C1E Enable |
| 180 | msr.lo |= (1 << 0); // Bi-directional PROCHOT# |
| 181 | wrmsr(MSR_POWER_CTL, msr); |
| 182 | |
| 183 | /* C3 Interrupt Response Time Limit */ |
| 184 | msr.hi = 0; |
| 185 | msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50; |
| 186 | wrmsr(MSR_PKGC3_IRTL, msr); |
| 187 | |
| 188 | /* C6 Interrupt Response Time Limit */ |
| 189 | msr.hi = 0; |
| 190 | msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68; |
| 191 | wrmsr(MSR_PKGC6_IRTL, msr); |
| 192 | |
| 193 | /* C7 Interrupt Response Time Limit */ |
| 194 | msr.hi = 0; |
| 195 | msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D; |
| 196 | wrmsr(MSR_PKGC7_IRTL, msr); |
| 197 | |
| 198 | /* Primary Plane Current Limit */ |
| 199 | msr = rdmsr(MSR_PP0_CURRENT_CONFIG); |
| 200 | msr.lo &= ~0x1fff; |
| 201 | msr.lo |= PP0_CURRENT_LIMIT; |
| 202 | wrmsr(MSR_PP0_CURRENT_CONFIG, msr); |
| 203 | |
| 204 | /* Secondary Plane Current Limit */ |
| 205 | msr = rdmsr(MSR_PP1_CURRENT_CONFIG); |
| 206 | msr.lo &= ~0x1fff; |
Duncan Laurie | 4e4320f | 2012-06-25 09:53:58 -0700 | [diff] [blame] | 207 | if (cpuid_eax(1) >= 0x30600) |
| 208 | msr.lo |= PP1_CURRENT_LIMIT_IVB; |
| 209 | else |
| 210 | msr.lo |= PP1_CURRENT_LIMIT_SNB; |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 211 | wrmsr(MSR_PP1_CURRENT_CONFIG, msr); |
| 212 | } |
| 213 | |
Arthur Heymans | cdb26fd | 2021-11-15 20:12:02 +0100 | [diff] [blame] | 214 | static void configure_thermal_target(struct device *dev) |
Duncan Laurie | 5563211 | 2012-07-16 12:19:00 -0700 | [diff] [blame] | 215 | { |
Arthur Heymans | cdb26fd | 2021-11-15 20:12:02 +0100 | [diff] [blame] | 216 | struct cpu_intel_model_206ax_config *conf = dev->bus->dev->chip_info; |
Duncan Laurie | 5563211 | 2012-07-16 12:19:00 -0700 | [diff] [blame] | 217 | msr_t msr; |
| 218 | |
Martin Roth | 4c3ab73 | 2013-07-08 16:23:54 -0600 | [diff] [blame] | 219 | /* Set TCC activation offset if supported */ |
Duncan Laurie | 5563211 | 2012-07-16 12:19:00 -0700 | [diff] [blame] | 220 | msr = rdmsr(MSR_PLATFORM_INFO); |
| 221 | if ((msr.lo & (1 << 30)) && conf->tcc_offset) { |
| 222 | msr = rdmsr(MSR_TEMPERATURE_TARGET); |
| 223 | msr.lo &= ~(0xf << 24); /* Bits 27:24 */ |
| 224 | msr.lo |= (conf->tcc_offset & 0xf) << 24; |
| 225 | wrmsr(MSR_TEMPERATURE_TARGET, msr); |
| 226 | } |
| 227 | } |
| 228 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 229 | static void configure_misc(void) |
| 230 | { |
| 231 | msr_t msr; |
| 232 | |
| 233 | msr = rdmsr(IA32_MISC_ENABLE); |
| 234 | msr.lo |= (1 << 0); /* Fast String enable */ |
Lee Leahy | 7b5f12b9 | 2017-03-15 17:16:59 -0700 | [diff] [blame] | 235 | msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 236 | msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ |
| 237 | wrmsr(IA32_MISC_ENABLE, msr); |
| 238 | |
| 239 | /* Disable Thermal interrupts */ |
| 240 | msr.lo = 0; |
| 241 | msr.hi = 0; |
| 242 | wrmsr(IA32_THERM_INTERRUPT, msr); |
| 243 | |
| 244 | /* Enable package critical interrupt only */ |
| 245 | msr.lo = 1 << 4; |
| 246 | msr.hi = 0; |
| 247 | wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); |
| 248 | } |
| 249 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 250 | static void set_max_ratio(void) |
| 251 | { |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 252 | msr_t msr, perf_ctl; |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 253 | |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 254 | perf_ctl.hi = 0; |
| 255 | |
| 256 | /* Check for configurable TDP option */ |
| 257 | if (cpu_config_tdp_levels()) { |
| 258 | /* Set to nominal TDP ratio */ |
| 259 | msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); |
| 260 | perf_ctl.lo = (msr.lo & 0xff) << 8; |
| 261 | } else { |
| 262 | /* Platform Info bits 15:8 give max ratio */ |
| 263 | msr = rdmsr(MSR_PLATFORM_INFO); |
| 264 | perf_ctl.lo = msr.lo & 0xff00; |
| 265 | } |
| 266 | wrmsr(IA32_PERF_CTL, perf_ctl); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 267 | |
| 268 | printk(BIOS_DEBUG, "model_x06ax: frequency set to %d\n", |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 269 | ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 270 | } |
| 271 | |
Michał Żygowski | 0d11dbf | 2020-10-31 21:43:25 +0100 | [diff] [blame] | 272 | unsigned int smbios_cpu_get_max_speed_mhz(void) |
| 273 | { |
| 274 | msr_t msr; |
| 275 | msr = rdmsr(MSR_TURBO_RATIO_LIMIT); |
| 276 | return (msr.lo & 0xff) * SANDYBRIDGE_BCLK; |
| 277 | } |
| 278 | |
| 279 | unsigned int smbios_cpu_get_current_speed_mhz(void) |
| 280 | { |
| 281 | msr_t msr; |
| 282 | msr = rdmsr(MSR_PLATFORM_INFO); |
| 283 | return ((msr.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK; |
| 284 | } |
| 285 | |
| 286 | unsigned int smbios_processor_external_clock(void) |
| 287 | { |
| 288 | return SANDYBRIDGE_BCLK; |
| 289 | } |
| 290 | |
Patrick Rudolph | 9e1b9b5 | 2018-07-27 17:25:05 +0200 | [diff] [blame] | 291 | static void model_206ax_report(void) |
| 292 | { |
| 293 | static const char *const mode[] = {"NOT ", ""}; |
Patrick Rudolph | 9e1b9b5 | 2018-07-27 17:25:05 +0200 | [diff] [blame] | 294 | char processor_name[49]; |
| 295 | int vt, txt, aes; |
Subrata Banik | 53b08c3 | 2018-12-10 14:11:35 +0530 | [diff] [blame] | 296 | uint32_t cpu_id, cpu_feature_flag; |
Patrick Rudolph | 9e1b9b5 | 2018-07-27 17:25:05 +0200 | [diff] [blame] | 297 | |
| 298 | /* Print processor name */ |
| 299 | fill_processor_name(processor_name); |
| 300 | printk(BIOS_INFO, "CPU: %s.\n", processor_name); |
| 301 | |
| 302 | /* Print platform ID */ |
| 303 | printk(BIOS_INFO, "CPU: platform id %x\n", get_platform_id()); |
| 304 | |
| 305 | /* CPUID and features */ |
Subrata Banik | 53b08c3 | 2018-12-10 14:11:35 +0530 | [diff] [blame] | 306 | cpu_id = cpu_get_cpuid(); |
| 307 | printk(BIOS_INFO, "CPU: cpuid(1) 0x%x\n", cpu_id); |
| 308 | |
| 309 | cpu_feature_flag = cpu_get_feature_flags_ecx(); |
| 310 | aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0; |
| 311 | txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0; |
| 312 | vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0; |
Patrick Rudolph | 9e1b9b5 | 2018-07-27 17:25:05 +0200 | [diff] [blame] | 313 | printk(BIOS_INFO, "CPU: AES %ssupported\n", mode[aes]); |
| 314 | printk(BIOS_INFO, "CPU: TXT %ssupported\n", mode[txt]); |
| 315 | printk(BIOS_INFO, "CPU: VT %ssupported\n", mode[vt]); |
| 316 | } |
| 317 | |
Edward O'Callaghan | 2c9d2cf | 2014-10-27 23:29:29 +1100 | [diff] [blame] | 318 | static void model_206ax_init(struct device *cpu) |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 319 | { |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 320 | /* Clear out pending MCEs */ |
Felix Held | acbf154 | 2021-07-13 16:44:18 +0200 | [diff] [blame] | 321 | /* This should only be done on a cold boot */ |
| 322 | mca_clear_status(); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 323 | |
Patrick Rudolph | 9e1b9b5 | 2018-07-27 17:25:05 +0200 | [diff] [blame] | 324 | /* Print infos */ |
| 325 | model_206ax_report(); |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 326 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 327 | /* Setup Page Attribute Tables (PAT) */ |
| 328 | // TODO set up PAT |
| 329 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 330 | enable_lapic_tpr(); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 331 | |
Matt DeVillier | ed6fe2f | 2016-12-14 16:12:43 -0600 | [diff] [blame] | 332 | /* Set virtualization based on Kconfig option */ |
Matt DeVillier | f9aed65 | 2018-12-15 15:57:33 -0600 | [diff] [blame] | 333 | set_vmx_and_lock(); |
Marc Jones | 5986eda | 2012-10-25 09:37:19 -0600 | [diff] [blame] | 334 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 335 | /* Configure C States */ |
| 336 | configure_c_states(); |
| 337 | |
| 338 | /* Configure Enhanced SpeedStep and Thermal Sensors */ |
| 339 | configure_misc(); |
| 340 | |
Duncan Laurie | 5563211 | 2012-07-16 12:19:00 -0700 | [diff] [blame] | 341 | /* Thermal throttle activation offset */ |
Arthur Heymans | cdb26fd | 2021-11-15 20:12:02 +0100 | [diff] [blame] | 342 | configure_thermal_target(cpu); |
Duncan Laurie | 5563211 | 2012-07-16 12:19:00 -0700 | [diff] [blame] | 343 | |
Michael Niewöhner | 6303243 | 2020-10-11 17:34:54 +0200 | [diff] [blame] | 344 | set_aesni_lock(); |
Michael Niewöhner | 7f8767d | 2020-10-18 00:45:38 +0200 | [diff] [blame] | 345 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 346 | /* Enable Direct Cache Access */ |
| 347 | configure_dca_cap(); |
| 348 | |
| 349 | /* Set energy policy */ |
| 350 | set_energy_perf_bias(ENERGY_POLICY_NORMAL); |
| 351 | |
| 352 | /* Set Max Ratio */ |
| 353 | set_max_ratio(); |
| 354 | |
| 355 | /* Enable Turbo */ |
| 356 | enable_turbo(); |
Arthur Heymans | edbf5d9 | 2018-01-25 20:03:42 +0100 | [diff] [blame] | 357 | } |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 358 | |
Arthur Heymans | edbf5d9 | 2018-01-25 20:03:42 +0100 | [diff] [blame] | 359 | /* MP initialization support. */ |
Arthur Heymans | edbf5d9 | 2018-01-25 20:03:42 +0100 | [diff] [blame] | 360 | static void pre_mp_init(void) |
| 361 | { |
| 362 | /* Setup MTRRs based on physical address size. */ |
| 363 | x86_setup_mtrrs_with_detect(); |
| 364 | x86_mtrr_check(); |
| 365 | } |
| 366 | |
| 367 | static int get_cpu_count(void) |
| 368 | { |
| 369 | msr_t msr; |
Angel Pons | 04c497a | 2021-11-03 16:30:10 +0100 | [diff] [blame] | 370 | unsigned int num_threads; |
| 371 | unsigned int num_cores; |
Arthur Heymans | edbf5d9 | 2018-01-25 20:03:42 +0100 | [diff] [blame] | 372 | |
Elyes HAOUAS | a6a396d | 2019-05-26 13:25:30 +0200 | [diff] [blame] | 373 | msr = rdmsr(MSR_CORE_THREAD_COUNT); |
Arthur Heymans | edbf5d9 | 2018-01-25 20:03:42 +0100 | [diff] [blame] | 374 | num_threads = (msr.lo >> 0) & 0xffff; |
| 375 | num_cores = (msr.lo >> 16) & 0xffff; |
| 376 | printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n", |
| 377 | num_cores, num_threads); |
| 378 | |
| 379 | return num_threads; |
| 380 | } |
| 381 | |
| 382 | static void get_microcode_info(const void **microcode, int *parallel) |
| 383 | { |
Patrick Rudolph | 3fa23b8 | 2021-01-25 09:42:08 +0100 | [diff] [blame] | 384 | *microcode = intel_microcode_find(); |
Patrick Rudolph | ce51b34 | 2021-01-11 09:21:58 +0100 | [diff] [blame] | 385 | *parallel = !intel_ht_supported(); |
Arthur Heymans | edbf5d9 | 2018-01-25 20:03:42 +0100 | [diff] [blame] | 386 | } |
| 387 | |
| 388 | static void per_cpu_smm_trigger(void) |
| 389 | { |
| 390 | /* Relocate the SMM handler. */ |
| 391 | smm_relocate(); |
| 392 | |
| 393 | /* After SMM relocation a 2nd microcode load is required. */ |
Patrick Rudolph | 3fa23b8 | 2021-01-25 09:42:08 +0100 | [diff] [blame] | 394 | const void *microcode_patch = intel_microcode_find(); |
Arthur Heymans | edbf5d9 | 2018-01-25 20:03:42 +0100 | [diff] [blame] | 395 | intel_microcode_load_unlocked(microcode_patch); |
| 396 | } |
| 397 | |
| 398 | static void post_mp_init(void) |
| 399 | { |
| 400 | /* Now that all APs have been relocated as well as the BSP let SMIs |
| 401 | * start flowing. */ |
Kyösti Mälkki | 0778c86 | 2020-06-10 12:44:03 +0300 | [diff] [blame] | 402 | global_smi_enable(); |
Arthur Heymans | edbf5d9 | 2018-01-25 20:03:42 +0100 | [diff] [blame] | 403 | |
| 404 | /* Lock down the SMRAM space. */ |
| 405 | smm_lock(); |
| 406 | } |
| 407 | |
Arthur Heymans | edbf5d9 | 2018-01-25 20:03:42 +0100 | [diff] [blame] | 408 | static const struct mp_ops mp_ops = { |
| 409 | .pre_mp_init = pre_mp_init, |
| 410 | .get_cpu_count = get_cpu_count, |
| 411 | .get_smm_info = smm_info, |
| 412 | .get_microcode_info = get_microcode_info, |
| 413 | .pre_mp_smm_init = smm_initialize, |
| 414 | .per_cpu_smm_trigger = per_cpu_smm_trigger, |
| 415 | .relocation_handler = smm_relocation_handler, |
| 416 | .post_mp_init = post_mp_init, |
| 417 | }; |
| 418 | |
Kyösti Mälkki | b3267e0 | 2019-08-13 16:44:04 +0300 | [diff] [blame] | 419 | void mp_init_cpus(struct bus *cpu_bus) |
Arthur Heymans | edbf5d9 | 2018-01-25 20:03:42 +0100 | [diff] [blame] | 420 | { |
Felix Held | 4dd7d11 | 2021-10-20 23:31:43 +0200 | [diff] [blame] | 421 | /* TODO: Handle mp_init_with_smm failure? */ |
| 422 | mp_init_with_smm(cpu_bus, &mp_ops); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 423 | } |
| 424 | |
| 425 | static struct device_operations cpu_dev_ops = { |
| 426 | .init = model_206ax_init, |
| 427 | }; |
| 428 | |
Jonathan Neuschäfer | 8f06ce3 | 2017-11-20 01:56:44 +0100 | [diff] [blame] | 429 | static const struct cpu_device_id cpu_table[] = { |
Felix Held | a5aee11 | 2023-02-06 17:01:59 +0100 | [diff] [blame^] | 430 | { X86_VENDOR_INTEL, 0x206a0, CPUID_ALL_STEPPINGS_MASK }, /* Intel Sandybridge */ |
| 431 | { X86_VENDOR_INTEL, 0x306a0, CPUID_ALL_STEPPINGS_MASK }, /* Intel IvyBridge */ |
Felix Held | 6a6ac1e | 2023-02-06 15:19:11 +0100 | [diff] [blame] | 432 | { 0, 0, 0 }, |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 433 | }; |
| 434 | |
| 435 | static const struct cpu_driver driver __cpu_driver = { |
| 436 | .ops = &cpu_dev_ops, |
| 437 | .id_table = cpu_table, |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 438 | }; |