Blame - src/southbridge/amd/pi/hudson/Kconfig - coreboot

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Elyes HAOUAS	8741510	2020-05-07 11:49:08 +0200	[diff] [blame]	1	# SPDX-License-Identifier: GPL-2.0-only
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	2
				3	config SOUTHBRIDGE_AMD_PI_AVALON
				4	bool
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	5
WANG Siyuan	f2dfef0	2015-05-20 14:41:01 +0800	[diff] [blame]	6	config SOUTHBRIDGE_AMD_PI_KERN
				7	bool
WANG Siyuan	f2dfef0	2015-05-20 14:41:01 +0800	[diff] [blame]	8
Felix Held	70d1c72	2021-04-09 22:22:09 +0200	[diff] [blame]	9	if SOUTHBRIDGE_AMD_PI_AVALON \|\| SOUTHBRIDGE_AMD_PI_KERN
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	10
Elyes HAOUAS	00b5f53	2021-02-01 09:45:08 +0100	[diff] [blame]	11	config SOUTHBRIDGE_SPECIFIC_OPTIONS
Nico Huber	f418105	2018-10-07 13:25:59 +0200	[diff] [blame]	12	def_bool y
Kyösti Mälkki	3454367	2023-04-08 23:07:57 +0300	[diff] [blame]	13	select ACPI_COMMON_MADT_IOAPIC
Kyösti Mälkki	69a1396	2023-04-08 14:10:48 +0300	[diff] [blame]	14	select ACPI_COMMON_MADT_LAPIC
Kyösti Mälkki	3454367	2023-04-08 23:07:57 +0300	[diff] [blame]	15	select ACPI_CUSTOM_MADT
Felix Held	78113d4	2024-01-08 17:09:09 +0100	[diff] [blame]	16	select HAVE_CONFIGURABLE_APMC_SMI_PORT
Nico Huber	f418105	2018-10-07 13:25:59 +0200	[diff] [blame]	17	select HAVE_USBDEBUG_OPTIONS
				18	select HAVE_CF9_RESET
				19	select HAVE_CF9_RESET_PREPARE
Michał Żygowski	f3db2ae	2019-11-24 13:26:10 +0100	[diff] [blame]	20	select SOC_AMD_COMMON
Michał Żygowski	f3db2ae	2019-11-24 13:26:10 +0100	[diff] [blame]	21	select SOC_AMD_COMMON_BLOCK_ACPIMMIO
Felix Held	3136424	2021-07-23 19:18:02 +0200	[diff] [blame]	22	select SOC_AMD_COMMON_BLOCK_ACPIMMIO_BIOSRAM
Felix Held	9ab8a78	2023-07-14 18:44:13 +0200	[diff] [blame]	23	select SOC_AMD_COMMON_BLOCK_ACPIMMIO_PM_IO_ACCESS
Kyösti Mälkki	b8cb142	2020-06-23 21:36:14 +0300	[diff] [blame]	24	select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
Felix Held	4b02769	2021-08-03 20:09:54 +0200	[diff] [blame]	25	select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS_NON_SOC_CODEBASE
Felix Held	21cdf0d	2020-11-23 16:24:29 +0100	[diff] [blame]	26	select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
Nico Huber	f418105	2018-10-07 13:25:59 +0200	[diff] [blame]	27
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	28	config EHCI_BAR
				29	hex
				30	default 0xfef00000
				31
				32	config HUDSON_XHCI_ENABLE
				33	bool "Enable Hudson XHCI Controller"
				34	default y
				35	help
				36	The XHCI controller must be enabled and the XHCI firmware
				37	must be added in order to have USB 3.0 support configured
				38	by coreboot. The OS will be responsible for enabling the XHCI
Jonathan Neuschäfer	45e6c82	2018-12-11 17:53:07 +0100	[diff] [blame]	39	controller if the XHCI firmware is available but the
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	40	XHCI controller is not enabled by coreboot.
				41
				42	config HUDSON_XHCI_FWM
				43	bool "Add xhci firmware"
				44	default y
				45	help
				46	Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0
				47
Mike Banon	7515cd0	2019-01-09 02:37:07 +0300	[diff] [blame]	48	config HUDSON_IMC_ENABLE
				49	bool
				50	default n
				51
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	52	config HUDSON_IMC_FWM
				53	bool "Add IMC firmware"
Mike Banon	7515cd0	2019-01-09 02:37:07 +0300	[diff] [blame]	54	depends on HUDSON_IMC_ENABLE
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	55	default y
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	56	help
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	57	Add Hudson 2/3/4 IMC Firmware to support the onboard fan control
				58
				59	config HUDSON_GEC_FWM
				60	bool
				61	default n
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	62	help
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	63	Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC.
				64	Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.
				65
				66	config HUDSON_PSP
				67	bool
Martin Roth	c681a82	2020-11-16 17:19:17 -0700	[diff] [blame]	68	default y if CPU_AMD_PI_00730F01
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	69
Zheng Bao	c5e28ab	2020-10-28 11:38:09 +0800	[diff] [blame]	70	config AMDFW_CONFIG_FILE
				71	string "AMD PSP Firmware config file"
				72	default "src/southbridge/amd/pi/hudson/fw_avl.cfg" if CPU_AMD_PI_00730F01
				73
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	74	config HUDSON_XHCI_FWM_FILE
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	75	string "XHCI firmware path and filename"
Patrick Georgi	26e24cc	2015-05-05 22:27:25 +0200	[diff] [blame]	76	default "3rdparty/blobs/southbridge/amd/avalon/xhci.bin" if SOUTHBRIDGE_AMD_PI_AVALON
WANG Siyuan	f2dfef0	2015-05-20 14:41:01 +0800	[diff] [blame]	77	default "3rdparty/blobs/southbridge/amd/kern/xhci.bin" if SOUTHBRIDGE_AMD_PI_KERN
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	78	depends on HUDSON_XHCI_FWM
				79
				80	config HUDSON_IMC_FWM_FILE
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	81	string "IMC firmware path and filename"
Patrick Georgi	26e24cc	2015-05-05 22:27:25 +0200	[diff] [blame]	82	default "3rdparty/blobs/southbridge/amd/avalon/imc.bin" if SOUTHBRIDGE_AMD_PI_AVALON
WANG Siyuan	f2dfef0	2015-05-20 14:41:01 +0800	[diff] [blame]	83	default "3rdparty/blobs/southbridge/amd/kern/imc.bin" if SOUTHBRIDGE_AMD_PI_KERN
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	84	depends on HUDSON_IMC_FWM
				85
				86	config HUDSON_GEC_FWM_FILE
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	87	string "GEC firmware path and filename"
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	88	depends on HUDSON_GEC_FWM
				89
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	90	config AMD_PUBKEY_FILE
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	91	depends on HUDSON_PSP
				92	string "AMD public Key"
Patrick Georgi	26e24cc	2015-05-05 22:27:25 +0200	[diff] [blame]	93	default "3rdparty/blobs/southbridge/amd/avalon/PSP/AmdPubKey.bin" if CPU_AMD_PI_00730F01
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	94
				95	config HUDSON_SATA_MODE
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	96	int "SATA Mode"
Piotr Kleinschmidt	cb03065	2019-10-08 16:16:44 +0200	[diff] [blame]	97	default 2
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	98	range 0 6
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	99	help
				100	Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
				101	The default is NATIVE.
				102	0: NATIVE mode does not require a ROM.
				103	1: RAID mode must have the two ROM files.
				104	2: AHCI may work with or without AHCI ROM. It depends on the payload support.
				105	For example, seabios does not require the AHCI ROM.
				106	3: LEGACY IDE
				107	4: IDE to AHCI
				108	5: AHCI7804: ROM Required, and AMD driver required in the OS.
				109	6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.
				110
				111	comment "NATIVE"
				112	depends on HUDSON_SATA_MODE = 0
				113
				114	comment "RAID"
				115	depends on HUDSON_SATA_MODE = 1
				116
				117	comment "AHCI"
				118	depends on HUDSON_SATA_MODE = 2
				119
				120	comment "LEGACY IDE"
				121	depends on HUDSON_SATA_MODE = 3
				122
				123	comment "IDE to AHCI"
				124	depends on HUDSON_SATA_MODE = 4
				125
				126	comment "AHCI7804"
				127	depends on HUDSON_SATA_MODE = 5
				128
				129	comment "IDE to AHCI7804"
				130	depends on HUDSON_SATA_MODE = 6
				131
Felix Held	02d2412	2024-01-10 21:54:22 +0100	[diff] [blame]	132	config HUDSON_FADT_LEGACY_DEVICES
				133	bool
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	134	help
Felix Held	02d2412	2024-01-10 21:54:22 +0100	[diff] [blame]	135	Select if there are legacy devices on the LPC bus.
				136
				137	config HUDSON_FADT_8042
				138	bool
				139	help
				140	Select if there is an 8042-compatible keyboard controller in the
				141	system.
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	142
Marshall Dawson	c6be0d8	2017-01-07 18:17:32 -0500	[diff] [blame]	143	config AMDFW_OUTSIDE_CBFS
				144	def_bool n
				145	help
				146	The AMDFW (PSP) is typically locatable in cbfs. Select this
				147	option to manually attach the generated amdfw.rom at an
				148	offset of 0x20000 from the bottom of the coreboot ROM image.
				149
Marc Jones	3eec9dd	2017-04-09 18:00:40 -0600	[diff] [blame]	150	config SERIRQ_CONTINUOUS_MODE
				151	bool
				152	default n
				153	help
				154	Set this option to y for serial IRQ in continuous mode.
				155	Otherwise it is in quiet mode.
Marc Jones	7f2c29b	2017-04-26 21:55:03 -0600	[diff] [blame]	156
				157	config HUDSON_ACPI_IO_BASE
				158	hex
Marc Jones	7f2c29b	2017-04-26 21:55:03 -0600	[diff] [blame]	159	default 0x800
				160	help
				161	Base address for the ACPI registers.
				162	This value must match the hardcoded value of AGESA.
				163
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	164	endif