Blame - src/southbridge/amd/pi/hudson/Kconfig - coreboot

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Elyes HAOUAS	8741510	2020-05-07 11:49:08 +0200	[diff] [blame]	1	# SPDX-License-Identifier: GPL-2.0-only
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	2
Dave Frodin	ef9a4e6	2015-01-27 07:16:03 -0700	[diff] [blame]	3	config SOUTHBRIDGE_AMD_PI_BOLTON
				4	bool
Dave Frodin	ef9a4e6	2015-01-27 07:16:03 -0700	[diff] [blame]	5
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	6	config SOUTHBRIDGE_AMD_PI_AVALON
				7	bool
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	8
WANG Siyuan	f2dfef0	2015-05-20 14:41:01 +0800	[diff] [blame]	9	config SOUTHBRIDGE_AMD_PI_KERN
				10	bool
WANG Siyuan	f2dfef0	2015-05-20 14:41:01 +0800	[diff] [blame]	11
				12	if SOUTHBRIDGE_AMD_PI_AVALON \|\| SOUTHBRIDGE_AMD_PI_BOLTON \|\| SOUTHBRIDGE_AMD_PI_KERN
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	13
Nico Huber	f418105	2018-10-07 13:25:59 +0200	[diff] [blame]	14	config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy
				15	def_bool y
				16	select IOAPIC
				17	select HAVE_USBDEBUG_OPTIONS
				18	select HAVE_CF9_RESET
				19	select HAVE_CF9_RESET_PREPARE
Michał Żygowski	f3db2ae	2019-11-24 13:26:10 +0100	[diff] [blame]	20	select SOC_AMD_COMMON
Michał Żygowski	f3db2ae	2019-11-24 13:26:10 +0100	[diff] [blame]	21	select SOC_AMD_COMMON_BLOCK_ACPIMMIO
Kyösti Mälkki	b8cb142	2020-06-23 21:36:14 +0300	[diff] [blame^]	22	select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
Felix Held	21cdf0d	2020-11-23 16:24:29 +0100	[diff] [blame]	23	select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
Nico Huber	f418105	2018-10-07 13:25:59 +0200	[diff] [blame]	24
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	25	config EHCI_BAR
				26	hex
				27	default 0xfef00000
				28
				29	config HUDSON_XHCI_ENABLE
				30	bool "Enable Hudson XHCI Controller"
				31	default y
				32	help
				33	The XHCI controller must be enabled and the XHCI firmware
				34	must be added in order to have USB 3.0 support configured
				35	by coreboot. The OS will be responsible for enabling the XHCI
Jonathan Neuschäfer	45e6c82	2018-12-11 17:53:07 +0100	[diff] [blame]	36	controller if the XHCI firmware is available but the
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	37	XHCI controller is not enabled by coreboot.
				38
				39	config HUDSON_XHCI_FWM
				40	bool "Add xhci firmware"
				41	default y
				42	help
				43	Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0
				44
Mike Banon	7515cd0	2019-01-09 02:37:07 +0300	[diff] [blame]	45	config HUDSON_IMC_ENABLE
				46	bool
				47	default n
				48
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	49	config HUDSON_IMC_FWM
				50	bool "Add IMC firmware"
Mike Banon	7515cd0	2019-01-09 02:37:07 +0300	[diff] [blame]	51	depends on HUDSON_IMC_ENABLE
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	52	default y
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	53	help
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	54	Add Hudson 2/3/4 IMC Firmware to support the onboard fan control
				55
				56	config HUDSON_GEC_FWM
				57	bool
				58	default n
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	59	help
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	60	Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC.
				61	Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.
				62
				63	config HUDSON_PSP
				64	bool
Martin Roth	c681a82	2020-11-16 17:19:17 -0700	[diff] [blame]	65	default y if CPU_AMD_PI_00730F01
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	66
Zheng Bao	c5e28ab	2020-10-28 11:38:09 +0800	[diff] [blame]	67	config AMDFW_CONFIG_FILE
				68	string "AMD PSP Firmware config file"
				69	default "src/southbridge/amd/pi/hudson/fw_avl.cfg" if CPU_AMD_PI_00730F01
				70
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	71	config HUDSON_XHCI_FWM_FILE
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	72	string "XHCI firmware path and filename"
Patrick Georgi	26e24cc	2015-05-05 22:27:25 +0200	[diff] [blame]	73	default "3rdparty/blobs/southbridge/amd/avalon/xhci.bin" if SOUTHBRIDGE_AMD_PI_AVALON
Kyösti Mälkki	841b2c8	2019-01-10 10:00:38 +0200	[diff] [blame]	74	default "3rdparty/blobs/southbridge/amd/bolton/xhci.bin" if SOUTHBRIDGE_AMD_PI_BOLTON
WANG Siyuan	f2dfef0	2015-05-20 14:41:01 +0800	[diff] [blame]	75	default "3rdparty/blobs/southbridge/amd/kern/xhci.bin" if SOUTHBRIDGE_AMD_PI_KERN
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	76	depends on HUDSON_XHCI_FWM
				77
				78	config HUDSON_IMC_FWM_FILE
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	79	string "IMC firmware path and filename"
Patrick Georgi	26e24cc	2015-05-05 22:27:25 +0200	[diff] [blame]	80	default "3rdparty/blobs/southbridge/amd/avalon/imc.bin" if SOUTHBRIDGE_AMD_PI_AVALON
Kyösti Mälkki	841b2c8	2019-01-10 10:00:38 +0200	[diff] [blame]	81	default "3rdparty/blobs/southbridge/amd/bolton/imc.bin" if SOUTHBRIDGE_AMD_PI_BOLTON
WANG Siyuan	f2dfef0	2015-05-20 14:41:01 +0800	[diff] [blame]	82	default "3rdparty/blobs/southbridge/amd/kern/imc.bin" if SOUTHBRIDGE_AMD_PI_KERN
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	83	depends on HUDSON_IMC_FWM
				84
				85	config HUDSON_GEC_FWM_FILE
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	86	string "GEC firmware path and filename"
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	87	depends on HUDSON_GEC_FWM
				88
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	89	config AMD_PUBKEY_FILE
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	90	depends on HUDSON_PSP
				91	string "AMD public Key"
Patrick Georgi	26e24cc	2015-05-05 22:27:25 +0200	[diff] [blame]	92	default "3rdparty/blobs/southbridge/amd/avalon/PSP/AmdPubKey.bin" if CPU_AMD_PI_00730F01
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	93
				94	config HUDSON_SATA_MODE
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	95	int "SATA Mode"
Piotr Kleinschmidt	cb03065	2019-10-08 16:16:44 +0200	[diff] [blame]	96	default 2
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	97	range 0 6
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	98	help
				99	Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
				100	The default is NATIVE.
				101	0: NATIVE mode does not require a ROM.
				102	1: RAID mode must have the two ROM files.
				103	2: AHCI may work with or without AHCI ROM. It depends on the payload support.
				104	For example, seabios does not require the AHCI ROM.
				105	3: LEGACY IDE
				106	4: IDE to AHCI
				107	5: AHCI7804: ROM Required, and AMD driver required in the OS.
				108	6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.
				109
				110	comment "NATIVE"
				111	depends on HUDSON_SATA_MODE = 0
				112
				113	comment "RAID"
				114	depends on HUDSON_SATA_MODE = 1
				115
				116	comment "AHCI"
				117	depends on HUDSON_SATA_MODE = 2
				118
				119	comment "LEGACY IDE"
				120	depends on HUDSON_SATA_MODE = 3
				121
				122	comment "IDE to AHCI"
				123	depends on HUDSON_SATA_MODE = 4
				124
				125	comment "AHCI7804"
				126	depends on HUDSON_SATA_MODE = 5
				127
				128	comment "IDE to AHCI7804"
				129	depends on HUDSON_SATA_MODE = 6
				130
				131	if HUDSON_SATA_MODE = 2 \|\| HUDSON_SATA_MODE = 5
				132
				133	config AHCI_ROM_ID
				134	string "AHCI device PCI IDs"
				135	default "1022,7801" if HUDSON_SATA_MODE = 2
				136	default "1022,7804" if HUDSON_SATA_MODE = 5
				137
				138	config HUDSON_AHCI_ROM
				139	bool "Add a AHCI ROM"
				140
				141	config AHCI_ROM_FILE
				142	string "AHCI ROM path and filename"
				143	depends on HUDSON_AHCI_ROM
Dave Frodin	bc21a41	2015-01-19 11:40:38 -0700	[diff] [blame]	144	default "src/southbridge/amd/pi/hudson/ahci.bin"
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	145
				146	endif
				147
				148	if HUDSON_SATA_MODE = 1
				149
				150	config RAID_ROM_ID
				151	string "RAID device PCI IDs"
				152	default "1022,7802"
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	153	help
				154	1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	155
				156	config RAID_ROM_FILE
				157	string "RAID ROM path and filename"
Dave Frodin	bc21a41	2015-01-19 11:40:38 -0700	[diff] [blame]	158	default "src/southbridge/amd/pi/hudson/raid.bin"
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	159
				160	config RAID_MISC_ROM_FILE
				161	string "RAID Misc ROM path and filename"
Dave Frodin	bc21a41	2015-01-19 11:40:38 -0700	[diff] [blame]	162	default "src/southbridge/amd/pi/hudson/misc.bin"
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	163
				164	config RAID_MISC_ROM_POSITION
				165	hex "RAID Misc ROM Position"
				166	default 0xFFF00000
				167	help
				168	The RAID ROM requires that the MISC ROM is located between the range
				169	0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
				170	The CONFIG_ROM_SIZE must be larger than 0x100000.
				171
				172	endif
				173
				174	config HUDSON_LEGACY_FREE
				175	bool "System is legacy free"
				176	help
				177	Select y if there is no keyboard controller in the system.
				178	This sets variables in AGESA and ACPI.
				179
				180	config AZ_PIN
				181	hex
				182	default 0xaa
				183	help
				184	bit 1,0 - pin 0
				185	bit 3,2 - pin 1
				186	bit 5,4 - pin 2
				187	bit 7,6 - pin 3
Marshall Dawson	c6be0d8	2017-01-07 18:17:32 -0500	[diff] [blame]	188
				189	config AMDFW_OUTSIDE_CBFS
				190	def_bool n
				191	help
				192	The AMDFW (PSP) is typically locatable in cbfs. Select this
				193	option to manually attach the generated amdfw.rom at an
				194	offset of 0x20000 from the bottom of the coreboot ROM image.
				195
Marc Jones	3eec9dd	2017-04-09 18:00:40 -0600	[diff] [blame]	196	config SERIRQ_CONTINUOUS_MODE
				197	bool
				198	default n
				199	help
				200	Set this option to y for serial IRQ in continuous mode.
				201	Otherwise it is in quiet mode.
Marc Jones	7f2c29b	2017-04-26 21:55:03 -0600	[diff] [blame]	202
				203	config HUDSON_ACPI_IO_BASE
				204	hex
Marc Jones	7f2c29b	2017-04-26 21:55:03 -0600	[diff] [blame]	205	default 0x800
				206	help
				207	Base address for the ACPI registers.
				208	This value must match the hardcoded value of AGESA.
				209
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	210	endif
Zheng Bao	2286138	2015-11-21 12:19:22 +0800	[diff] [blame]	211
				212	config HUDSON_UART
Zheng Bao	e1e9ed3	2015-12-07 22:59:45 +0800	[diff] [blame]	213	bool "UART controller on Kern"
Zheng Bao	2286138	2015-11-21 12:19:22 +0800	[diff] [blame]	214	default n
				215	depends on SOUTHBRIDGE_AMD_PI_KERN
				216	select DRIVERS_UART_8250MEM
				217	select DRIVERS_UART_8250MEM_32
				218	select NO_UART_ON_SUPERIO
Lee Leahy	6ec72c9	2016-05-07 09:04:46 -0700	[diff] [blame]	219	select UART_OVERRIDE_REFCLK
Zheng Bao	2286138	2015-11-21 12:19:22 +0800	[diff] [blame]	220	help
				221	There are two UART controllers in Kern.
				222	The UART registers are memory-mapped. UART
				223	controller 0 registers range from FEDC_6000h
				224	to FEDC_6FFFh. UART controller 1 registers
				225	range from FEDC_8000h to FEDC_8FFFh.