Gitiles
Code Review Sign In
review.coreboot.org / coreboot / 69a13964ea6c5fda6ddf475a9ea905aa7376620c / . / src / southbridge / amd / pi / hudson / Kconfig
blob: 4b194319249a361472719c5d2238ef585412eb37 [file] [log] [blame]
Elyes HAOUAS87415102020-05-07 11:49:08 +0200[diff] [blame]1# SPDX-License-Identifier: GPL-2.0-only
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]2
3config SOUTHBRIDGE_AMD_PI_AVALON
4 bool
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]5
WANG Siyuanf2dfef02015-05-20 14:41:01 +0800[diff] [blame]6config SOUTHBRIDGE_AMD_PI_KERN
7 bool
WANG Siyuanf2dfef02015-05-20 14:41:01 +0800[diff] [blame]8
Felix Held70d1c722021-04-09 22:22:09 +0200[diff] [blame]9if SOUTHBRIDGE_AMD_PI_AVALON || SOUTHBRIDGE_AMD_PI_KERN
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]10
Elyes HAOUAS00b5f532021-02-01 09:45:08 +0100[diff] [blame]11config SOUTHBRIDGE_SPECIFIC_OPTIONS
Nico Huberf4181052018-10-07 13:25:59 +0200[diff] [blame]12 def_bool y
Kyösti Mälkki69a13962023-04-08 14:10:48 +0300[diff] [blame^]13 select ACPI_COMMON_MADT_LAPIC
Nico Huberf4181052018-10-07 13:25:59 +0200[diff] [blame]14 select HAVE_USBDEBUG_OPTIONS
15 select HAVE_CF9_RESET
16 select HAVE_CF9_RESET_PREPARE
Michał Żygowskif3db2ae2019-11-24 13:26:10 +0100[diff] [blame]17 select SOC_AMD_COMMON
Michał Żygowskif3db2ae2019-11-24 13:26:10 +0100[diff] [blame]18 select SOC_AMD_COMMON_BLOCK_ACPIMMIO
Felix Held31364242021-07-23 19:18:02 +0200[diff] [blame]19 select SOC_AMD_COMMON_BLOCK_ACPIMMIO_BIOSRAM
Kyösti Mälkkib8cb1422020-06-23 21:36:14 +0300[diff] [blame]20 select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
Felix Held4b027692021-08-03 20:09:54 +0200[diff] [blame]21 select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS_NON_SOC_CODEBASE
Felix Held21cdf0d2020-11-23 16:24:29 +0100[diff] [blame]22 select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
Nico Huberf4181052018-10-07 13:25:59 +0200[diff] [blame]23
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]24config EHCI_BAR
25 hex
26 default 0xfef00000
27
28config HUDSON_XHCI_ENABLE
29 bool "Enable Hudson XHCI Controller"
30 default y
31 help
32 The XHCI controller must be enabled and the XHCI firmware
33 must be added in order to have USB 3.0 support configured
34 by coreboot. The OS will be responsible for enabling the XHCI
Jonathan Neuschäfer45e6c822018-12-11 17:53:07 +0100[diff] [blame]35 controller if the XHCI firmware is available but the
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]36 XHCI controller is not enabled by coreboot.
37
38config HUDSON_XHCI_FWM
39 bool "Add xhci firmware"
40 default y
41 help
42 Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0
43
Mike Banon7515cd02019-01-09 02:37:07 +0300[diff] [blame]44config HUDSON_IMC_ENABLE
45 bool
46 default n
47
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]48config HUDSON_IMC_FWM
49 bool "Add IMC firmware"
Mike Banon7515cd02019-01-09 02:37:07 +0300[diff] [blame]50 depends on HUDSON_IMC_ENABLE
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]51 default y
Dave Frodinfedd8e32015-01-21 07:26:26 -0700[diff] [blame]52 help
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]53 Add Hudson 2/3/4 IMC Firmware to support the onboard fan control
54
55config HUDSON_GEC_FWM
56 bool
57 default n
Dave Frodinfedd8e32015-01-21 07:26:26 -0700[diff] [blame]58 help
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]59 Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC.
60 Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.
61
62config HUDSON_PSP
63 bool
Martin Rothc681a822020-11-16 17:19:17 -0700[diff] [blame]64 default y if CPU_AMD_PI_00730F01
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]65
Zheng Baoc5e28ab2020-10-28 11:38:09 +0800[diff] [blame]66config AMDFW_CONFIG_FILE
67 string "AMD PSP Firmware config file"
68 default "src/southbridge/amd/pi/hudson/fw_avl.cfg" if CPU_AMD_PI_00730F01
69
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]70config HUDSON_XHCI_FWM_FILE
Dave Frodinfedd8e32015-01-21 07:26:26 -0700[diff] [blame]71 string "XHCI firmware path and filename"
Patrick Georgi26e24cc2015-05-05 22:27:25 +0200[diff] [blame]72 default "3rdparty/blobs/southbridge/amd/avalon/xhci.bin" if SOUTHBRIDGE_AMD_PI_AVALON
WANG Siyuanf2dfef02015-05-20 14:41:01 +0800[diff] [blame]73 default "3rdparty/blobs/southbridge/amd/kern/xhci.bin" if SOUTHBRIDGE_AMD_PI_KERN
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]74 depends on HUDSON_XHCI_FWM
75
76config HUDSON_IMC_FWM_FILE
Dave Frodinfedd8e32015-01-21 07:26:26 -0700[diff] [blame]77 string "IMC firmware path and filename"
Patrick Georgi26e24cc2015-05-05 22:27:25 +0200[diff] [blame]78 default "3rdparty/blobs/southbridge/amd/avalon/imc.bin" if SOUTHBRIDGE_AMD_PI_AVALON
WANG Siyuanf2dfef02015-05-20 14:41:01 +0800[diff] [blame]79 default "3rdparty/blobs/southbridge/amd/kern/imc.bin" if SOUTHBRIDGE_AMD_PI_KERN
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]80 depends on HUDSON_IMC_FWM
81
82config HUDSON_GEC_FWM_FILE
Dave Frodinfedd8e32015-01-21 07:26:26 -0700[diff] [blame]83 string "GEC firmware path and filename"
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]84 depends on HUDSON_GEC_FWM
85
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]86config AMD_PUBKEY_FILE
Dave Frodinfedd8e32015-01-21 07:26:26 -0700[diff] [blame]87 depends on HUDSON_PSP
88 string "AMD public Key"
Patrick Georgi26e24cc2015-05-05 22:27:25 +0200[diff] [blame]89 default "3rdparty/blobs/southbridge/amd/avalon/PSP/AmdPubKey.bin" if CPU_AMD_PI_00730F01
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]90
91config HUDSON_SATA_MODE
Dave Frodinfedd8e32015-01-21 07:26:26 -0700[diff] [blame]92 int "SATA Mode"
Piotr Kleinschmidtcb030652019-10-08 16:16:44 +0200[diff] [blame]93 default 2
Dave Frodinfedd8e32015-01-21 07:26:26 -0700[diff] [blame]94 range 0 6
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]95 help
96 Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
97 The default is NATIVE.
98 0: NATIVE mode does not require a ROM.
99 1: RAID mode must have the two ROM files.
100 2: AHCI may work with or without AHCI ROM. It depends on the payload support.
101 For example, seabios does not require the AHCI ROM.
102 3: LEGACY IDE
103 4: IDE to AHCI
104 5: AHCI7804: ROM Required, and AMD driver required in the OS.
105 6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.
106
107comment "NATIVE"
108 depends on HUDSON_SATA_MODE = 0
109
110comment "RAID"
111 depends on HUDSON_SATA_MODE = 1
112
113comment "AHCI"
114 depends on HUDSON_SATA_MODE = 2
115
116comment "LEGACY IDE"
117 depends on HUDSON_SATA_MODE = 3
118
119comment "IDE to AHCI"
120 depends on HUDSON_SATA_MODE = 4
121
122comment "AHCI7804"
123 depends on HUDSON_SATA_MODE = 5
124
125comment "IDE to AHCI7804"
126 depends on HUDSON_SATA_MODE = 6
127
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]128config HUDSON_LEGACY_FREE
129 bool "System is legacy free"
130 help
131 Select y if there is no keyboard controller in the system.
132 This sets variables in AGESA and ACPI.
133
Marshall Dawsonc6be0d82017-01-07 18:17:32 -0500[diff] [blame]134config AMDFW_OUTSIDE_CBFS
135 def_bool n
136 help
137 The AMDFW (PSP) is typically locatable in cbfs. Select this
138 option to manually attach the generated amdfw.rom at an
139 offset of 0x20000 from the bottom of the coreboot ROM image.
140
Marc Jones3eec9dd2017-04-09 18:00:40 -0600[diff] [blame]141config SERIRQ_CONTINUOUS_MODE
142 bool
143 default n
144 help
145 Set this option to y for serial IRQ in continuous mode.
146 Otherwise it is in quiet mode.
Marc Jones7f2c29b2017-04-26 21:55:03 -0600[diff] [blame]147
148config HUDSON_ACPI_IO_BASE
149 hex
Marc Jones7f2c29b2017-04-26 21:55:03 -0600[diff] [blame]150 default 0x800
151 help
152 Base address for the ACPI registers.
153 This value must match the hardcoded value of AGESA.
154
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]155endif