Blame - src/southbridge/amd/pi/hudson/Kconfig - coreboot

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Elyes HAOUAS	8741510	2020-05-07 11:49:08 +0200	[diff] [blame]	1	# SPDX-License-Identifier: GPL-2.0-only
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	2
Dave Frodin	ef9a4e6	2015-01-27 07:16:03 -0700	[diff] [blame]	3	config SOUTHBRIDGE_AMD_PI_BOLTON
				4	bool
Dave Frodin	ef9a4e6	2015-01-27 07:16:03 -0700	[diff] [blame]	5
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	6	config SOUTHBRIDGE_AMD_PI_AVALON
				7	bool
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	8
WANG Siyuan	f2dfef0	2015-05-20 14:41:01 +0800	[diff] [blame]	9	config SOUTHBRIDGE_AMD_PI_KERN
				10	bool
WANG Siyuan	f2dfef0	2015-05-20 14:41:01 +0800	[diff] [blame]	11
				12	if SOUTHBRIDGE_AMD_PI_AVALON \|\| SOUTHBRIDGE_AMD_PI_BOLTON \|\| SOUTHBRIDGE_AMD_PI_KERN
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	13
Nico Huber	f418105	2018-10-07 13:25:59 +0200	[diff] [blame]	14	config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy
				15	def_bool y
				16	select IOAPIC
				17	select HAVE_USBDEBUG_OPTIONS
				18	select HAVE_CF9_RESET
				19	select HAVE_CF9_RESET_PREPARE
Michał Żygowski	f3db2ae	2019-11-24 13:26:10 +0100	[diff] [blame]	20	select SOC_AMD_COMMON
Michał Żygowski	f3db2ae	2019-11-24 13:26:10 +0100	[diff] [blame]	21	select SOC_AMD_COMMON_BLOCK_ACPIMMIO
Nico Huber	f418105	2018-10-07 13:25:59 +0200	[diff] [blame]	22
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	23	config EHCI_BAR
				24	hex
				25	default 0xfef00000
				26
				27	config HUDSON_XHCI_ENABLE
				28	bool "Enable Hudson XHCI Controller"
				29	default y
				30	help
				31	The XHCI controller must be enabled and the XHCI firmware
				32	must be added in order to have USB 3.0 support configured
				33	by coreboot. The OS will be responsible for enabling the XHCI
Jonathan Neuschäfer	45e6c82	2018-12-11 17:53:07 +0100	[diff] [blame]	34	controller if the XHCI firmware is available but the
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	35	XHCI controller is not enabled by coreboot.
				36
				37	config HUDSON_XHCI_FWM
				38	bool "Add xhci firmware"
				39	default y
				40	help
				41	Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0
				42
Mike Banon	7515cd0	2019-01-09 02:37:07 +0300	[diff] [blame]	43	config HUDSON_IMC_ENABLE
				44	bool
				45	default n
				46
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	47	config HUDSON_IMC_FWM
				48	bool "Add IMC firmware"
Mike Banon	7515cd0	2019-01-09 02:37:07 +0300	[diff] [blame]	49	depends on HUDSON_IMC_ENABLE
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	50	default y
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	51	help
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	52	Add Hudson 2/3/4 IMC Firmware to support the onboard fan control
				53
				54	config HUDSON_GEC_FWM
				55	bool
				56	default n
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	57	help
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	58	Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC.
				59	Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.
				60
				61	config HUDSON_PSP
				62	bool
Martin Roth	c681a82	2020-11-16 17:19:17 -0700	[diff] [blame^]	63	default y if CPU_AMD_PI_00730F01
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	64
Zheng Bao	c5e28ab	2020-10-28 11:38:09 +0800	[diff] [blame]	65	config AMDFW_CONFIG_FILE
				66	string "AMD PSP Firmware config file"
				67	default "src/southbridge/amd/pi/hudson/fw_avl.cfg" if CPU_AMD_PI_00730F01
				68
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	69	config HUDSON_XHCI_FWM_FILE
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	70	string "XHCI firmware path and filename"
Patrick Georgi	26e24cc	2015-05-05 22:27:25 +0200	[diff] [blame]	71	default "3rdparty/blobs/southbridge/amd/avalon/xhci.bin" if SOUTHBRIDGE_AMD_PI_AVALON
Kyösti Mälkki	841b2c8	2019-01-10 10:00:38 +0200	[diff] [blame]	72	default "3rdparty/blobs/southbridge/amd/bolton/xhci.bin" if SOUTHBRIDGE_AMD_PI_BOLTON
WANG Siyuan	f2dfef0	2015-05-20 14:41:01 +0800	[diff] [blame]	73	default "3rdparty/blobs/southbridge/amd/kern/xhci.bin" if SOUTHBRIDGE_AMD_PI_KERN
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	74	depends on HUDSON_XHCI_FWM
				75
				76	config HUDSON_IMC_FWM_FILE
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	77	string "IMC firmware path and filename"
Patrick Georgi	26e24cc	2015-05-05 22:27:25 +0200	[diff] [blame]	78	default "3rdparty/blobs/southbridge/amd/avalon/imc.bin" if SOUTHBRIDGE_AMD_PI_AVALON
Kyösti Mälkki	841b2c8	2019-01-10 10:00:38 +0200	[diff] [blame]	79	default "3rdparty/blobs/southbridge/amd/bolton/imc.bin" if SOUTHBRIDGE_AMD_PI_BOLTON
WANG Siyuan	f2dfef0	2015-05-20 14:41:01 +0800	[diff] [blame]	80	default "3rdparty/blobs/southbridge/amd/kern/imc.bin" if SOUTHBRIDGE_AMD_PI_KERN
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	81	depends on HUDSON_IMC_FWM
				82
				83	config HUDSON_GEC_FWM_FILE
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	84	string "GEC firmware path and filename"
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	85	depends on HUDSON_GEC_FWM
				86
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	87	config AMD_PUBKEY_FILE
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	88	depends on HUDSON_PSP
				89	string "AMD public Key"
Patrick Georgi	26e24cc	2015-05-05 22:27:25 +0200	[diff] [blame]	90	default "3rdparty/blobs/southbridge/amd/avalon/PSP/AmdPubKey.bin" if CPU_AMD_PI_00730F01
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	91
				92	config HUDSON_SATA_MODE
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	93	int "SATA Mode"
Piotr Kleinschmidt	cb03065	2019-10-08 16:16:44 +0200	[diff] [blame]	94	default 2
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	95	range 0 6
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	96	help
				97	Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
				98	The default is NATIVE.
				99	0: NATIVE mode does not require a ROM.
				100	1: RAID mode must have the two ROM files.
				101	2: AHCI may work with or without AHCI ROM. It depends on the payload support.
				102	For example, seabios does not require the AHCI ROM.
				103	3: LEGACY IDE
				104	4: IDE to AHCI
				105	5: AHCI7804: ROM Required, and AMD driver required in the OS.
				106	6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.
				107
				108	comment "NATIVE"
				109	depends on HUDSON_SATA_MODE = 0
				110
				111	comment "RAID"
				112	depends on HUDSON_SATA_MODE = 1
				113
				114	comment "AHCI"
				115	depends on HUDSON_SATA_MODE = 2
				116
				117	comment "LEGACY IDE"
				118	depends on HUDSON_SATA_MODE = 3
				119
				120	comment "IDE to AHCI"
				121	depends on HUDSON_SATA_MODE = 4
				122
				123	comment "AHCI7804"
				124	depends on HUDSON_SATA_MODE = 5
				125
				126	comment "IDE to AHCI7804"
				127	depends on HUDSON_SATA_MODE = 6
				128
				129	if HUDSON_SATA_MODE = 2 \|\| HUDSON_SATA_MODE = 5
				130
				131	config AHCI_ROM_ID
				132	string "AHCI device PCI IDs"
				133	default "1022,7801" if HUDSON_SATA_MODE = 2
				134	default "1022,7804" if HUDSON_SATA_MODE = 5
				135
				136	config HUDSON_AHCI_ROM
				137	bool "Add a AHCI ROM"
				138
				139	config AHCI_ROM_FILE
				140	string "AHCI ROM path and filename"
				141	depends on HUDSON_AHCI_ROM
Dave Frodin	bc21a41	2015-01-19 11:40:38 -0700	[diff] [blame]	142	default "src/southbridge/amd/pi/hudson/ahci.bin"
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	143
				144	endif
				145
				146	if HUDSON_SATA_MODE = 1
				147
				148	config RAID_ROM_ID
				149	string "RAID device PCI IDs"
				150	default "1022,7802"
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	151	help
				152	1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	153
				154	config RAID_ROM_FILE
				155	string "RAID ROM path and filename"
Dave Frodin	bc21a41	2015-01-19 11:40:38 -0700	[diff] [blame]	156	default "src/southbridge/amd/pi/hudson/raid.bin"
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	157
				158	config RAID_MISC_ROM_FILE
				159	string "RAID Misc ROM path and filename"
Dave Frodin	bc21a41	2015-01-19 11:40:38 -0700	[diff] [blame]	160	default "src/southbridge/amd/pi/hudson/misc.bin"
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	161
				162	config RAID_MISC_ROM_POSITION
				163	hex "RAID Misc ROM Position"
				164	default 0xFFF00000
				165	help
				166	The RAID ROM requires that the MISC ROM is located between the range
				167	0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
				168	The CONFIG_ROM_SIZE must be larger than 0x100000.
				169
				170	endif
				171
				172	config HUDSON_LEGACY_FREE
				173	bool "System is legacy free"
				174	help
				175	Select y if there is no keyboard controller in the system.
				176	This sets variables in AGESA and ACPI.
				177
				178	config AZ_PIN
				179	hex
				180	default 0xaa
				181	help
				182	bit 1,0 - pin 0
				183	bit 3,2 - pin 1
				184	bit 5,4 - pin 2
				185	bit 7,6 - pin 3
Marshall Dawson	c6be0d8	2017-01-07 18:17:32 -0500	[diff] [blame]	186
				187	config AMDFW_OUTSIDE_CBFS
				188	def_bool n
				189	help
				190	The AMDFW (PSP) is typically locatable in cbfs. Select this
				191	option to manually attach the generated amdfw.rom at an
				192	offset of 0x20000 from the bottom of the coreboot ROM image.
				193
Marc Jones	3eec9dd	2017-04-09 18:00:40 -0600	[diff] [blame]	194	config SERIRQ_CONTINUOUS_MODE
				195	bool
				196	default n
				197	help
				198	Set this option to y for serial IRQ in continuous mode.
				199	Otherwise it is in quiet mode.
Marc Jones	7f2c29b	2017-04-26 21:55:03 -0600	[diff] [blame]	200
				201	config HUDSON_ACPI_IO_BASE
				202	hex
Marc Jones	7f2c29b	2017-04-26 21:55:03 -0600	[diff] [blame]	203	default 0x800
				204	help
				205	Base address for the ACPI registers.
				206	This value must match the hardcoded value of AGESA.
				207
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	208	endif
Zheng Bao	2286138	2015-11-21 12:19:22 +0800	[diff] [blame]	209
				210	config HUDSON_UART
Zheng Bao	e1e9ed3	2015-12-07 22:59:45 +0800	[diff] [blame]	211	bool "UART controller on Kern"
Zheng Bao	2286138	2015-11-21 12:19:22 +0800	[diff] [blame]	212	default n
				213	depends on SOUTHBRIDGE_AMD_PI_KERN
				214	select DRIVERS_UART_8250MEM
				215	select DRIVERS_UART_8250MEM_32
				216	select NO_UART_ON_SUPERIO
Lee Leahy	6ec72c9	2016-05-07 09:04:46 -0700	[diff] [blame]	217	select UART_OVERRIDE_REFCLK
Zheng Bao	2286138	2015-11-21 12:19:22 +0800	[diff] [blame]	218	help
				219	There are two UART controllers in Kern.
				220	The UART registers are memory-mapped. UART
				221	controller 0 registers range from FEDC_6000h
				222	to FEDC_6FFFh. UART controller 1 registers
				223	range from FEDC_8000h to FEDC_8FFFh.