Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
Marc Jones | a84fa90 | 2016-09-20 20:33:42 -0600 | [diff] [blame] | 4 | ## Copyright (C) 2010-2016 Advanced Micro Devices, Inc. |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 5 | ## |
| 6 | ## This program is free software; you can redistribute it and/or modify |
| 7 | ## it under the terms of the GNU General Public License as published by |
| 8 | ## the Free Software Foundation; version 2 of the License. |
| 9 | ## |
| 10 | ## This program is distributed in the hope that it will be useful, |
| 11 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | ## GNU General Public License for more details. |
| 14 | ## |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 15 | |
Dave Frodin | ef9a4e6 | 2015-01-27 07:16:03 -0700 | [diff] [blame] | 16 | config SOUTHBRIDGE_AMD_PI_BOLTON |
| 17 | bool |
Dave Frodin | ef9a4e6 | 2015-01-27 07:16:03 -0700 | [diff] [blame] | 18 | |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 19 | config SOUTHBRIDGE_AMD_PI_AVALON |
| 20 | bool |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 21 | |
WANG Siyuan | f2dfef0 | 2015-05-20 14:41:01 +0800 | [diff] [blame] | 22 | config SOUTHBRIDGE_AMD_PI_KERN |
| 23 | bool |
WANG Siyuan | f2dfef0 | 2015-05-20 14:41:01 +0800 | [diff] [blame] | 24 | |
| 25 | if SOUTHBRIDGE_AMD_PI_AVALON || SOUTHBRIDGE_AMD_PI_BOLTON || SOUTHBRIDGE_AMD_PI_KERN |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 26 | |
Nico Huber | f418105 | 2018-10-07 13:25:59 +0200 | [diff] [blame] | 27 | config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy |
| 28 | def_bool y |
| 29 | select IOAPIC |
| 30 | select HAVE_USBDEBUG_OPTIONS |
| 31 | select HAVE_CF9_RESET |
| 32 | select HAVE_CF9_RESET_PREPARE |
| 33 | |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 34 | config BOOTBLOCK_SOUTHBRIDGE_INIT |
| 35 | string |
Dave Frodin | bc21a41 | 2015-01-19 11:40:38 -0700 | [diff] [blame] | 36 | default "southbridge/amd/pi/hudson/bootblock.c" |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 37 | |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 38 | config EHCI_BAR |
| 39 | hex |
| 40 | default 0xfef00000 |
| 41 | |
| 42 | config HUDSON_XHCI_ENABLE |
| 43 | bool "Enable Hudson XHCI Controller" |
| 44 | default y |
| 45 | help |
| 46 | The XHCI controller must be enabled and the XHCI firmware |
| 47 | must be added in order to have USB 3.0 support configured |
| 48 | by coreboot. The OS will be responsible for enabling the XHCI |
Jonathan Neuschäfer | 45e6c82 | 2018-12-11 17:53:07 +0100 | [diff] [blame] | 49 | controller if the XHCI firmware is available but the |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 50 | XHCI controller is not enabled by coreboot. |
| 51 | |
| 52 | config HUDSON_XHCI_FWM |
| 53 | bool "Add xhci firmware" |
| 54 | default y |
| 55 | help |
| 56 | Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0 |
| 57 | |
Mike Banon | 7515cd0 | 2019-01-09 02:37:07 +0300 | [diff] [blame^] | 58 | config HUDSON_IMC_ENABLE |
| 59 | bool |
| 60 | default n |
| 61 | |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 62 | config HUDSON_IMC_FWM |
| 63 | bool "Add IMC firmware" |
Mike Banon | 7515cd0 | 2019-01-09 02:37:07 +0300 | [diff] [blame^] | 64 | depends on HUDSON_IMC_ENABLE |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 65 | default y |
Dave Frodin | fedd8e3 | 2015-01-21 07:26:26 -0700 | [diff] [blame] | 66 | help |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 67 | Add Hudson 2/3/4 IMC Firmware to support the onboard fan control |
| 68 | |
| 69 | config HUDSON_GEC_FWM |
| 70 | bool |
| 71 | default n |
Dave Frodin | fedd8e3 | 2015-01-21 07:26:26 -0700 | [diff] [blame] | 72 | help |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 73 | Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC. |
| 74 | Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard. |
| 75 | |
| 76 | config HUDSON_PSP |
| 77 | bool |
Kyösti Mälkki | fa2786a | 2017-07-07 23:05:40 +0300 | [diff] [blame] | 78 | default y if CPU_AMD_PI_00730F01 || CPU_AMD_PI_00660F01 |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 79 | |
| 80 | config HUDSON_XHCI_FWM_FILE |
Dave Frodin | fedd8e3 | 2015-01-21 07:26:26 -0700 | [diff] [blame] | 81 | string "XHCI firmware path and filename" |
Patrick Georgi | 26e24cc | 2015-05-05 22:27:25 +0200 | [diff] [blame] | 82 | default "3rdparty/blobs/southbridge/amd/avalon/xhci.bin" if SOUTHBRIDGE_AMD_PI_AVALON |
WANG Siyuan | f2dfef0 | 2015-05-20 14:41:01 +0800 | [diff] [blame] | 83 | default "3rdparty/blobs/southbridge/amd/kern/xhci.bin" if SOUTHBRIDGE_AMD_PI_KERN |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 84 | depends on HUDSON_XHCI_FWM |
| 85 | |
| 86 | config HUDSON_IMC_FWM_FILE |
Dave Frodin | fedd8e3 | 2015-01-21 07:26:26 -0700 | [diff] [blame] | 87 | string "IMC firmware path and filename" |
Patrick Georgi | 26e24cc | 2015-05-05 22:27:25 +0200 | [diff] [blame] | 88 | default "3rdparty/blobs/southbridge/amd/avalon/imc.bin" if SOUTHBRIDGE_AMD_PI_AVALON |
WANG Siyuan | f2dfef0 | 2015-05-20 14:41:01 +0800 | [diff] [blame] | 89 | default "3rdparty/blobs/southbridge/amd/kern/imc.bin" if SOUTHBRIDGE_AMD_PI_KERN |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 90 | depends on HUDSON_IMC_FWM |
| 91 | |
| 92 | config HUDSON_GEC_FWM_FILE |
Dave Frodin | fedd8e3 | 2015-01-21 07:26:26 -0700 | [diff] [blame] | 93 | string "GEC firmware path and filename" |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 94 | depends on HUDSON_GEC_FWM |
| 95 | |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 96 | config AMD_PUBKEY_FILE |
Dave Frodin | fedd8e3 | 2015-01-21 07:26:26 -0700 | [diff] [blame] | 97 | depends on HUDSON_PSP |
| 98 | string "AMD public Key" |
Patrick Georgi | 26e24cc | 2015-05-05 22:27:25 +0200 | [diff] [blame] | 99 | default "3rdparty/blobs/southbridge/amd/avalon/PSP/AmdPubKey.bin" if CPU_AMD_PI_00730F01 |
WANG Siyuan | f2dfef0 | 2015-05-20 14:41:01 +0800 | [diff] [blame] | 100 | default "3rdparty/blobs/southbridge/amd/kern/PSP/AmdPubKeyCZ.bin" if CPU_AMD_PI_00660F01 |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 101 | |
| 102 | config HUDSON_SATA_MODE |
Dave Frodin | fedd8e3 | 2015-01-21 07:26:26 -0700 | [diff] [blame] | 103 | int "SATA Mode" |
| 104 | default 0 |
| 105 | range 0 6 |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 106 | help |
| 107 | Select the mode in which SATA should be driven. NATIVE AHCI, or RAID. |
| 108 | The default is NATIVE. |
| 109 | 0: NATIVE mode does not require a ROM. |
| 110 | 1: RAID mode must have the two ROM files. |
| 111 | 2: AHCI may work with or without AHCI ROM. It depends on the payload support. |
| 112 | For example, seabios does not require the AHCI ROM. |
| 113 | 3: LEGACY IDE |
| 114 | 4: IDE to AHCI |
| 115 | 5: AHCI7804: ROM Required, and AMD driver required in the OS. |
| 116 | 6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS. |
| 117 | |
| 118 | comment "NATIVE" |
| 119 | depends on HUDSON_SATA_MODE = 0 |
| 120 | |
| 121 | comment "RAID" |
| 122 | depends on HUDSON_SATA_MODE = 1 |
| 123 | |
| 124 | comment "AHCI" |
| 125 | depends on HUDSON_SATA_MODE = 2 |
| 126 | |
| 127 | comment "LEGACY IDE" |
| 128 | depends on HUDSON_SATA_MODE = 3 |
| 129 | |
| 130 | comment "IDE to AHCI" |
| 131 | depends on HUDSON_SATA_MODE = 4 |
| 132 | |
| 133 | comment "AHCI7804" |
| 134 | depends on HUDSON_SATA_MODE = 5 |
| 135 | |
| 136 | comment "IDE to AHCI7804" |
| 137 | depends on HUDSON_SATA_MODE = 6 |
| 138 | |
| 139 | if HUDSON_SATA_MODE = 2 || HUDSON_SATA_MODE = 5 |
| 140 | |
| 141 | config AHCI_ROM_ID |
| 142 | string "AHCI device PCI IDs" |
| 143 | default "1022,7801" if HUDSON_SATA_MODE = 2 |
| 144 | default "1022,7804" if HUDSON_SATA_MODE = 5 |
| 145 | |
| 146 | config HUDSON_AHCI_ROM |
| 147 | bool "Add a AHCI ROM" |
| 148 | |
| 149 | config AHCI_ROM_FILE |
| 150 | string "AHCI ROM path and filename" |
| 151 | depends on HUDSON_AHCI_ROM |
Dave Frodin | bc21a41 | 2015-01-19 11:40:38 -0700 | [diff] [blame] | 152 | default "src/southbridge/amd/pi/hudson/ahci.bin" |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 153 | |
| 154 | endif |
| 155 | |
| 156 | if HUDSON_SATA_MODE = 1 |
| 157 | |
| 158 | config RAID_ROM_ID |
| 159 | string "RAID device PCI IDs" |
| 160 | default "1022,7802" |
Dave Frodin | fedd8e3 | 2015-01-21 07:26:26 -0700 | [diff] [blame] | 161 | help |
| 162 | 1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 163 | |
| 164 | config RAID_ROM_FILE |
| 165 | string "RAID ROM path and filename" |
Dave Frodin | bc21a41 | 2015-01-19 11:40:38 -0700 | [diff] [blame] | 166 | default "src/southbridge/amd/pi/hudson/raid.bin" |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 167 | |
| 168 | config RAID_MISC_ROM_FILE |
| 169 | string "RAID Misc ROM path and filename" |
Dave Frodin | bc21a41 | 2015-01-19 11:40:38 -0700 | [diff] [blame] | 170 | default "src/southbridge/amd/pi/hudson/misc.bin" |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 171 | |
| 172 | config RAID_MISC_ROM_POSITION |
| 173 | hex "RAID Misc ROM Position" |
| 174 | default 0xFFF00000 |
| 175 | help |
| 176 | The RAID ROM requires that the MISC ROM is located between the range |
| 177 | 0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned. |
| 178 | The CONFIG_ROM_SIZE must be larger than 0x100000. |
| 179 | |
| 180 | endif |
| 181 | |
| 182 | config HUDSON_LEGACY_FREE |
| 183 | bool "System is legacy free" |
| 184 | help |
| 185 | Select y if there is no keyboard controller in the system. |
| 186 | This sets variables in AGESA and ACPI. |
| 187 | |
| 188 | config AZ_PIN |
| 189 | hex |
| 190 | default 0xaa |
| 191 | help |
| 192 | bit 1,0 - pin 0 |
| 193 | bit 3,2 - pin 1 |
| 194 | bit 5,4 - pin 2 |
| 195 | bit 7,6 - pin 3 |
Marshall Dawson | c6be0d8 | 2017-01-07 18:17:32 -0500 | [diff] [blame] | 196 | |
| 197 | config AMDFW_OUTSIDE_CBFS |
| 198 | def_bool n |
| 199 | help |
| 200 | The AMDFW (PSP) is typically locatable in cbfs. Select this |
| 201 | option to manually attach the generated amdfw.rom at an |
| 202 | offset of 0x20000 from the bottom of the coreboot ROM image. |
| 203 | |
Marc Jones | 3eec9dd | 2017-04-09 18:00:40 -0600 | [diff] [blame] | 204 | config SERIRQ_CONTINUOUS_MODE |
| 205 | bool |
| 206 | default n |
| 207 | help |
| 208 | Set this option to y for serial IRQ in continuous mode. |
| 209 | Otherwise it is in quiet mode. |
Marc Jones | 7f2c29b | 2017-04-26 21:55:03 -0600 | [diff] [blame] | 210 | |
| 211 | config HUDSON_ACPI_IO_BASE |
| 212 | hex |
Marc Jones | 7f2c29b | 2017-04-26 21:55:03 -0600 | [diff] [blame] | 213 | default 0x800 |
| 214 | help |
| 215 | Base address for the ACPI registers. |
| 216 | This value must match the hardcoded value of AGESA. |
| 217 | |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 218 | endif |
Zheng Bao | 2286138 | 2015-11-21 12:19:22 +0800 | [diff] [blame] | 219 | |
| 220 | config HUDSON_UART |
Zheng Bao | e1e9ed3 | 2015-12-07 22:59:45 +0800 | [diff] [blame] | 221 | bool "UART controller on Kern" |
Zheng Bao | 2286138 | 2015-11-21 12:19:22 +0800 | [diff] [blame] | 222 | default n |
| 223 | depends on SOUTHBRIDGE_AMD_PI_KERN |
| 224 | select DRIVERS_UART_8250MEM |
| 225 | select DRIVERS_UART_8250MEM_32 |
| 226 | select NO_UART_ON_SUPERIO |
Lee Leahy | 6ec72c9 | 2016-05-07 09:04:46 -0700 | [diff] [blame] | 227 | select UART_OVERRIDE_REFCLK |
Zheng Bao | 2286138 | 2015-11-21 12:19:22 +0800 | [diff] [blame] | 228 | help |
| 229 | There are two UART controllers in Kern. |
| 230 | The UART registers are memory-mapped. UART |
| 231 | controller 0 registers range from FEDC_6000h |
| 232 | to FEDC_6FFFh. UART controller 1 registers |
| 233 | range from FEDC_8000h to FEDC_8FFFh. |