Blame - src/southbridge/amd/pi/hudson/Kconfig - coreboot

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Elyes HAOUAS	8741510	2020-05-07 11:49:08 +0200	[diff] [blame]	1	# SPDX-License-Identifier: GPL-2.0-only
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	2
				3	config SOUTHBRIDGE_AMD_PI_AVALON
				4	bool
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	5
WANG Siyuan	f2dfef0	2015-05-20 14:41:01 +0800	[diff] [blame]	6	config SOUTHBRIDGE_AMD_PI_KERN
				7	bool
WANG Siyuan	f2dfef0	2015-05-20 14:41:01 +0800	[diff] [blame]	8
Felix Held	70d1c72	2021-04-09 22:22:09 +0200	[diff] [blame]	9	if SOUTHBRIDGE_AMD_PI_AVALON \|\| SOUTHBRIDGE_AMD_PI_KERN
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	10
Elyes HAOUAS	00b5f53	2021-02-01 09:45:08 +0100	[diff] [blame]	11	config SOUTHBRIDGE_SPECIFIC_OPTIONS
Nico Huber	f418105	2018-10-07 13:25:59 +0200	[diff] [blame]	12	def_bool y
				13	select IOAPIC
				14	select HAVE_USBDEBUG_OPTIONS
				15	select HAVE_CF9_RESET
				16	select HAVE_CF9_RESET_PREPARE
Michał Żygowski	f3db2ae	2019-11-24 13:26:10 +0100	[diff] [blame]	17	select SOC_AMD_COMMON
Michał Żygowski	f3db2ae	2019-11-24 13:26:10 +0100	[diff] [blame]	18	select SOC_AMD_COMMON_BLOCK_ACPIMMIO
Felix Held	3136424	2021-07-23 19:18:02 +0200	[diff] [blame^]	19	select SOC_AMD_COMMON_BLOCK_ACPIMMIO_BIOSRAM
Kyösti Mälkki	b8cb142	2020-06-23 21:36:14 +0300	[diff] [blame]	20	select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
Felix Held	21cdf0d	2020-11-23 16:24:29 +0100	[diff] [blame]	21	select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
Nico Huber	f418105	2018-10-07 13:25:59 +0200	[diff] [blame]	22
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	23	config EHCI_BAR
				24	hex
				25	default 0xfef00000
				26
				27	config HUDSON_XHCI_ENABLE
				28	bool "Enable Hudson XHCI Controller"
				29	default y
				30	help
				31	The XHCI controller must be enabled and the XHCI firmware
				32	must be added in order to have USB 3.0 support configured
				33	by coreboot. The OS will be responsible for enabling the XHCI
Jonathan Neuschäfer	45e6c82	2018-12-11 17:53:07 +0100	[diff] [blame]	34	controller if the XHCI firmware is available but the
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	35	XHCI controller is not enabled by coreboot.
				36
				37	config HUDSON_XHCI_FWM
				38	bool "Add xhci firmware"
				39	default y
				40	help
				41	Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0
				42
Mike Banon	7515cd0	2019-01-09 02:37:07 +0300	[diff] [blame]	43	config HUDSON_IMC_ENABLE
				44	bool
				45	default n
				46
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	47	config HUDSON_IMC_FWM
				48	bool "Add IMC firmware"
Mike Banon	7515cd0	2019-01-09 02:37:07 +0300	[diff] [blame]	49	depends on HUDSON_IMC_ENABLE
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	50	default y
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	51	help
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	52	Add Hudson 2/3/4 IMC Firmware to support the onboard fan control
				53
				54	config HUDSON_GEC_FWM
				55	bool
				56	default n
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	57	help
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	58	Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC.
				59	Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.
				60
				61	config HUDSON_PSP
				62	bool
Martin Roth	c681a82	2020-11-16 17:19:17 -0700	[diff] [blame]	63	default y if CPU_AMD_PI_00730F01
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	64
Zheng Bao	c5e28ab	2020-10-28 11:38:09 +0800	[diff] [blame]	65	config AMDFW_CONFIG_FILE
				66	string "AMD PSP Firmware config file"
				67	default "src/southbridge/amd/pi/hudson/fw_avl.cfg" if CPU_AMD_PI_00730F01
				68
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	69	config HUDSON_XHCI_FWM_FILE
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	70	string "XHCI firmware path and filename"
Patrick Georgi	26e24cc	2015-05-05 22:27:25 +0200	[diff] [blame]	71	default "3rdparty/blobs/southbridge/amd/avalon/xhci.bin" if SOUTHBRIDGE_AMD_PI_AVALON
WANG Siyuan	f2dfef0	2015-05-20 14:41:01 +0800	[diff] [blame]	72	default "3rdparty/blobs/southbridge/amd/kern/xhci.bin" if SOUTHBRIDGE_AMD_PI_KERN
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	73	depends on HUDSON_XHCI_FWM
				74
				75	config HUDSON_IMC_FWM_FILE
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	76	string "IMC firmware path and filename"
Patrick Georgi	26e24cc	2015-05-05 22:27:25 +0200	[diff] [blame]	77	default "3rdparty/blobs/southbridge/amd/avalon/imc.bin" if SOUTHBRIDGE_AMD_PI_AVALON
WANG Siyuan	f2dfef0	2015-05-20 14:41:01 +0800	[diff] [blame]	78	default "3rdparty/blobs/southbridge/amd/kern/imc.bin" if SOUTHBRIDGE_AMD_PI_KERN
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	79	depends on HUDSON_IMC_FWM
				80
				81	config HUDSON_GEC_FWM_FILE
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	82	string "GEC firmware path and filename"
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	83	depends on HUDSON_GEC_FWM
				84
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	85	config AMD_PUBKEY_FILE
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	86	depends on HUDSON_PSP
				87	string "AMD public Key"
Patrick Georgi	26e24cc	2015-05-05 22:27:25 +0200	[diff] [blame]	88	default "3rdparty/blobs/southbridge/amd/avalon/PSP/AmdPubKey.bin" if CPU_AMD_PI_00730F01
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	89
				90	config HUDSON_SATA_MODE
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	91	int "SATA Mode"
Piotr Kleinschmidt	cb03065	2019-10-08 16:16:44 +0200	[diff] [blame]	92	default 2
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	93	range 0 6
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	94	help
				95	Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
				96	The default is NATIVE.
				97	0: NATIVE mode does not require a ROM.
				98	1: RAID mode must have the two ROM files.
				99	2: AHCI may work with or without AHCI ROM. It depends on the payload support.
				100	For example, seabios does not require the AHCI ROM.
				101	3: LEGACY IDE
				102	4: IDE to AHCI
				103	5: AHCI7804: ROM Required, and AMD driver required in the OS.
				104	6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.
				105
				106	comment "NATIVE"
				107	depends on HUDSON_SATA_MODE = 0
				108
				109	comment "RAID"
				110	depends on HUDSON_SATA_MODE = 1
				111
				112	comment "AHCI"
				113	depends on HUDSON_SATA_MODE = 2
				114
				115	comment "LEGACY IDE"
				116	depends on HUDSON_SATA_MODE = 3
				117
				118	comment "IDE to AHCI"
				119	depends on HUDSON_SATA_MODE = 4
				120
				121	comment "AHCI7804"
				122	depends on HUDSON_SATA_MODE = 5
				123
				124	comment "IDE to AHCI7804"
				125	depends on HUDSON_SATA_MODE = 6
				126
				127	if HUDSON_SATA_MODE = 2 \|\| HUDSON_SATA_MODE = 5
				128
				129	config AHCI_ROM_ID
				130	string "AHCI device PCI IDs"
				131	default "1022,7801" if HUDSON_SATA_MODE = 2
				132	default "1022,7804" if HUDSON_SATA_MODE = 5
				133
				134	config HUDSON_AHCI_ROM
				135	bool "Add a AHCI ROM"
				136
				137	config AHCI_ROM_FILE
				138	string "AHCI ROM path and filename"
				139	depends on HUDSON_AHCI_ROM
Dave Frodin	bc21a41	2015-01-19 11:40:38 -0700	[diff] [blame]	140	default "src/southbridge/amd/pi/hudson/ahci.bin"
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	141
				142	endif
				143
				144	if HUDSON_SATA_MODE = 1
				145
				146	config RAID_ROM_ID
				147	string "RAID device PCI IDs"
				148	default "1022,7802"
Dave Frodin	fedd8e3	2015-01-21 07:26:26 -0700	[diff] [blame]	149	help
				150	1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	151
				152	config RAID_ROM_FILE
				153	string "RAID ROM path and filename"
Dave Frodin	bc21a41	2015-01-19 11:40:38 -0700	[diff] [blame]	154	default "src/southbridge/amd/pi/hudson/raid.bin"
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	155
				156	config RAID_MISC_ROM_FILE
				157	string "RAID Misc ROM path and filename"
Dave Frodin	bc21a41	2015-01-19 11:40:38 -0700	[diff] [blame]	158	default "src/southbridge/amd/pi/hudson/misc.bin"
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	159
				160	config RAID_MISC_ROM_POSITION
				161	hex "RAID Misc ROM Position"
				162	default 0xFFF00000
				163	help
				164	The RAID ROM requires that the MISC ROM is located between the range
				165	0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
				166	The CONFIG_ROM_SIZE must be larger than 0x100000.
				167
				168	endif
				169
				170	config HUDSON_LEGACY_FREE
				171	bool "System is legacy free"
				172	help
				173	Select y if there is no keyboard controller in the system.
				174	This sets variables in AGESA and ACPI.
				175
				176	config AZ_PIN
				177	hex
				178	default 0xaa
				179	help
				180	bit 1,0 - pin 0
				181	bit 3,2 - pin 1
				182	bit 5,4 - pin 2
				183	bit 7,6 - pin 3
Marshall Dawson	c6be0d8	2017-01-07 18:17:32 -0500	[diff] [blame]	184
				185	config AMDFW_OUTSIDE_CBFS
				186	def_bool n
				187	help
				188	The AMDFW (PSP) is typically locatable in cbfs. Select this
				189	option to manually attach the generated amdfw.rom at an
				190	offset of 0x20000 from the bottom of the coreboot ROM image.
				191
Marc Jones	3eec9dd	2017-04-09 18:00:40 -0600	[diff] [blame]	192	config SERIRQ_CONTINUOUS_MODE
				193	bool
				194	default n
				195	help
				196	Set this option to y for serial IRQ in continuous mode.
				197	Otherwise it is in quiet mode.
Marc Jones	7f2c29b	2017-04-26 21:55:03 -0600	[diff] [blame]	198
				199	config HUDSON_ACPI_IO_BASE
				200	hex
Marc Jones	7f2c29b	2017-04-26 21:55:03 -0600	[diff] [blame]	201	default 0x800
				202	help
				203	Base address for the ACPI registers.
				204	This value must match the hardcoded value of AGESA.
				205
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	206	endif
Zheng Bao	2286138	2015-11-21 12:19:22 +0800	[diff] [blame]	207
				208	config HUDSON_UART
Zheng Bao	e1e9ed3	2015-12-07 22:59:45 +0800	[diff] [blame]	209	bool "UART controller on Kern"
Zheng Bao	2286138	2015-11-21 12:19:22 +0800	[diff] [blame]	210	default n
				211	depends on SOUTHBRIDGE_AMD_PI_KERN
				212	select DRIVERS_UART_8250MEM
				213	select DRIVERS_UART_8250MEM_32
				214	select NO_UART_ON_SUPERIO
Lee Leahy	6ec72c9	2016-05-07 09:04:46 -0700	[diff] [blame]	215	select UART_OVERRIDE_REFCLK
Zheng Bao	2286138	2015-11-21 12:19:22 +0800	[diff] [blame]	216	help
				217	There are two UART controllers in Kern.
				218	The UART registers are memory-mapped. UART
				219	controller 0 registers range from FEDC_6000h
				220	to FEDC_6FFFh. UART controller 1 registers
				221	range from FEDC_8000h to FEDC_8FFFh.