Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame^] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | ## |
| 6 | ## This program is free software; you can redistribute it and/or modify |
| 7 | ## it under the terms of the GNU General Public License as published by |
| 8 | ## the Free Software Foundation; version 2 of the License. |
| 9 | ## |
| 10 | ## This program is distributed in the hope that it will be useful, |
| 11 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | ## GNU General Public License for more details. |
| 14 | ## |
| 15 | ## You should have received a copy of the GNU General Public License |
| 16 | ## along with this program; if not, write to the Free Software |
| 17 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | ## |
| 19 | |
| 20 | config SOUTHBRIDGE_AMD_PI_AVALON |
| 21 | bool |
| 22 | select IOAPIC |
| 23 | select HAVE_USBDEBUG_OPTIONS |
| 24 | select HAVE_HARD_RESET |
| 25 | |
| 26 | if SOUTHBRIDGE_AMD_PI_AVALON |
| 27 | |
| 28 | config BOOTBLOCK_SOUTHBRIDGE_INIT |
| 29 | string |
| 30 | default "southbridge/amd/pi/avalon/bootblock.c" |
| 31 | |
| 32 | config SOUTHBRIDGE_AMD_HUDSON_SKIP_ISA_DMA_INIT |
| 33 | bool |
| 34 | default n |
| 35 | |
| 36 | config EHCI_BAR |
| 37 | hex |
| 38 | default 0xfef00000 |
| 39 | |
| 40 | config HUDSON_XHCI_ENABLE |
| 41 | bool "Enable Hudson XHCI Controller" |
| 42 | default y |
| 43 | help |
| 44 | The XHCI controller must be enabled and the XHCI firmware |
| 45 | must be added in order to have USB 3.0 support configured |
| 46 | by coreboot. The OS will be responsible for enabling the XHCI |
| 47 | controller if the the XHCI firmware is available but the |
| 48 | XHCI controller is not enabled by coreboot. |
| 49 | |
| 50 | config HUDSON_XHCI_FWM |
| 51 | bool "Add xhci firmware" |
| 52 | default y |
| 53 | help |
| 54 | Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0 |
| 55 | |
| 56 | config HUDSON_DISABLE_IMC |
| 57 | bool |
| 58 | default n |
| 59 | |
| 60 | config HUDSON_IMC_FWM |
| 61 | bool "Add IMC firmware" |
| 62 | depends on !HUDSON_DISABLE_IMC |
| 63 | default y |
| 64 | help |
| 65 | Add Hudson 2/3/4 IMC Firmware to support the onboard fan control |
| 66 | |
| 67 | config HUDSON_GEC_FWM |
| 68 | bool |
| 69 | default n |
| 70 | help |
| 71 | Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC. |
| 72 | Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard. |
| 73 | |
| 74 | config HUDSON_PSP |
| 75 | bool |
| 76 | default y if CPU_AMD_PI_00730F01 |
| 77 | |
| 78 | config HUDSON_XHCI_FWM_FILE |
| 79 | string "XHCI firmware path and filename" |
| 80 | default "3rdparty/southbridge/amd/avalon/xhci.bin" if SOUTHBRIDGE_AMD_PI_AVALON |
| 81 | depends on HUDSON_XHCI_FWM |
| 82 | |
| 83 | config HUDSON_IMC_FWM_FILE |
| 84 | string "IMC firmware path and filename" |
| 85 | default "3rdparty/southbridge/amd/avalon/imc.bin" if SOUTHBRIDGE_AMD_PI_AVALON |
| 86 | depends on HUDSON_IMC_FWM |
| 87 | |
| 88 | config HUDSON_GEC_FWM_FILE |
| 89 | string "GEC firmware path and filename" |
| 90 | depends on HUDSON_GEC_FWM |
| 91 | |
| 92 | config HUDSON_FWM |
| 93 | bool |
| 94 | default y if HUDSON_XHCI_FWM || HUDSON_IMC_FWM || HUDSON_GEC_FWM || HUDSON_PSP |
| 95 | default n |
| 96 | |
| 97 | if HUDSON_FWM |
| 98 | |
| 99 | config HUDSON_FWM_POSITION |
| 100 | hex "Hudson Firmware ROM Position" |
| 101 | default 0xFFF20000 if BOARD_ROMSIZE_KB_1024 |
| 102 | default 0xFFE20000 if BOARD_ROMSIZE_KB_2048 |
| 103 | default 0xFFC20000 if BOARD_ROMSIZE_KB_4096 |
| 104 | default 0xFF820000 if BOARD_ROMSIZE_KB_8192 |
| 105 | default 0xFF020000 if BOARD_ROMSIZE_KB_16384 |
| 106 | help |
| 107 | Hudson requires the firmware MUST be located at |
| 108 | a specific address (ROM start address + 0x20000), otherwise |
| 109 | xhci host Controller can not find or load the xhci firmware. |
| 110 | |
| 111 | The firmware start address is dependent on the ROM chip size. |
| 112 | The default offset is 0x20000 from the ROM start address, namely |
| 113 | 0xFFF20000 if flash chip size is 1M |
| 114 | 0xFFE20000 if flash chip size is 2M |
| 115 | 0xFFC20000 if flash chip size is 4M |
| 116 | 0xFF820000 if flash chip size is 8M |
| 117 | 0xFF020000 if flash chip size is 16M |
| 118 | endif # HUDSON_FWM |
| 119 | |
| 120 | config AMD_PUBKEY_FILE |
| 121 | depends on HUDSON_PSP |
| 122 | string "AMD public Key" |
| 123 | default "3rdparty/southbridge/amd/avalon/PSP/AmdPubKey.bin" if CPU_AMD_PI_00730F01 |
| 124 | |
| 125 | config HUDSON_SATA_MODE |
| 126 | int "SATA Mode" |
| 127 | default 0 |
| 128 | range 0 6 |
| 129 | help |
| 130 | Select the mode in which SATA should be driven. NATIVE AHCI, or RAID. |
| 131 | The default is NATIVE. |
| 132 | 0: NATIVE mode does not require a ROM. |
| 133 | 1: RAID mode must have the two ROM files. |
| 134 | 2: AHCI may work with or without AHCI ROM. It depends on the payload support. |
| 135 | For example, seabios does not require the AHCI ROM. |
| 136 | 3: LEGACY IDE |
| 137 | 4: IDE to AHCI |
| 138 | 5: AHCI7804: ROM Required, and AMD driver required in the OS. |
| 139 | 6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS. |
| 140 | |
| 141 | comment "NATIVE" |
| 142 | depends on HUDSON_SATA_MODE = 0 |
| 143 | |
| 144 | comment "RAID" |
| 145 | depends on HUDSON_SATA_MODE = 1 |
| 146 | |
| 147 | comment "AHCI" |
| 148 | depends on HUDSON_SATA_MODE = 2 |
| 149 | |
| 150 | comment "LEGACY IDE" |
| 151 | depends on HUDSON_SATA_MODE = 3 |
| 152 | |
| 153 | comment "IDE to AHCI" |
| 154 | depends on HUDSON_SATA_MODE = 4 |
| 155 | |
| 156 | comment "AHCI7804" |
| 157 | depends on HUDSON_SATA_MODE = 5 |
| 158 | |
| 159 | comment "IDE to AHCI7804" |
| 160 | depends on HUDSON_SATA_MODE = 6 |
| 161 | |
| 162 | if HUDSON_SATA_MODE = 2 || HUDSON_SATA_MODE = 5 |
| 163 | |
| 164 | config AHCI_ROM_ID |
| 165 | string "AHCI device PCI IDs" |
| 166 | default "1022,7801" if HUDSON_SATA_MODE = 2 |
| 167 | default "1022,7804" if HUDSON_SATA_MODE = 5 |
| 168 | |
| 169 | config HUDSON_AHCI_ROM |
| 170 | bool "Add a AHCI ROM" |
| 171 | |
| 172 | config AHCI_ROM_FILE |
| 173 | string "AHCI ROM path and filename" |
| 174 | depends on HUDSON_AHCI_ROM |
| 175 | default "src/southbridge/amd/agesa/hudson/ahci.bin" |
| 176 | |
| 177 | endif |
| 178 | |
| 179 | if HUDSON_SATA_MODE = 1 |
| 180 | |
| 181 | config RAID_ROM_ID |
| 182 | string "RAID device PCI IDs" |
| 183 | default "1022,7802" |
| 184 | help |
| 185 | 1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode |
| 186 | |
| 187 | config RAID_ROM_FILE |
| 188 | string "RAID ROM path and filename" |
| 189 | default "src/southbridge/amd/agesa/hudson/raid.bin" |
| 190 | |
| 191 | config RAID_MISC_ROM_FILE |
| 192 | string "RAID Misc ROM path and filename" |
| 193 | default "src/southbridge/amd/agesa/hudson/misc.bin" |
| 194 | |
| 195 | config RAID_MISC_ROM_POSITION |
| 196 | hex "RAID Misc ROM Position" |
| 197 | default 0xFFF00000 |
| 198 | help |
| 199 | The RAID ROM requires that the MISC ROM is located between the range |
| 200 | 0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned. |
| 201 | The CONFIG_ROM_SIZE must be larger than 0x100000. |
| 202 | |
| 203 | endif |
| 204 | |
| 205 | config HUDSON_LEGACY_FREE |
| 206 | bool "System is legacy free" |
| 207 | help |
| 208 | Select y if there is no keyboard controller in the system. |
| 209 | This sets variables in AGESA and ACPI. |
| 210 | |
| 211 | config AZ_PIN |
| 212 | hex |
| 213 | default 0xaa |
| 214 | help |
| 215 | bit 1,0 - pin 0 |
| 216 | bit 3,2 - pin 1 |
| 217 | bit 5,4 - pin 2 |
| 218 | bit 7,6 - pin 3 |
| 219 | endif |