Felix Held | 4a8cd72 | 2020-04-18 22:26:39 +0200 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 2 | |
Marshall Dawson | 6851922 | 2019-11-25 11:36:15 -0700 | [diff] [blame] | 3 | config SOC_AMD_STONEYRIDGE |
| 4 | bool |
Kyösti Mälkki | 3139c8d | 2020-06-28 16:33:33 +0300 | [diff] [blame] | 5 | select ACPI_SOC_NVS |
Angel Pons | 8e035e3 | 2021-06-22 12:58:20 +0200 | [diff] [blame] | 6 | select ARCH_X86 |
Felix Held | c07c7c9 | 2020-12-04 18:50:53 +0100 | [diff] [blame] | 7 | select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH |
Aaron Durbin | 51e4c1a | 2018-01-24 17:42:51 -0700 | [diff] [blame] | 8 | select COLLECT_TIMESTAMPS_NO_TSC |
Marc Jones | 9156cac | 2017-07-12 11:05:38 -0600 | [diff] [blame] | 9 | select GENERIC_GPIO_LIB |
Aaron Durbin | 51e4c1a | 2018-01-24 17:42:51 -0700 | [diff] [blame] | 10 | select GENERIC_UDELAY |
Angel Pons | b74975e | 2020-07-13 01:12:57 +0200 | [diff] [blame] | 11 | select HAVE_CF9_RESET |
Felix Held | c07c7c9 | 2020-12-04 18:50:53 +0100 | [diff] [blame] | 12 | select HAVE_SMI_HANDLER |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 13 | select HAVE_USBDEBUG_OPTIONS |
Marc Jones | 33eef13 | 2017-10-26 16:50:42 -0600 | [diff] [blame] | 14 | select PARALLEL_MP_AP_WORK |
Marc Jones | 17e85ad | 2017-12-20 16:21:25 -0700 | [diff] [blame] | 15 | select RTC |
Felix Held | c07c7c9 | 2020-12-04 18:50:53 +0100 | [diff] [blame] | 16 | select SOC_AMD_PI |
| 17 | select SOC_AMD_COMMON |
| 18 | select SOC_AMD_COMMON_BLOCK_ACPI |
Felix Held | 0bc4684 | 2021-11-23 10:19:28 +0100 | [diff] [blame] | 19 | select SOC_AMD_COMMON_BLOCK_ACPI_GPIO |
Felix Held | fc709fe | 2023-03-24 21:41:35 +0100 | [diff] [blame] | 20 | select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE |
Felix Held | 590d2d5 | 2024-01-09 17:04:17 +0100 | [diff] [blame] | 21 | select SOC_AMD_COMMON_BLOCK_ACPI_MADT |
Felix Held | c07c7c9 | 2020-12-04 18:50:53 +0100 | [diff] [blame] | 22 | select SOC_AMD_COMMON_BLOCK_ACPIMMIO |
Felix Held | 3136424 | 2021-07-23 19:18:02 +0200 | [diff] [blame] | 23 | select SOC_AMD_COMMON_BLOCK_ACPIMMIO_BIOSRAM |
Felix Held | 9ab8a78 | 2023-07-14 18:44:13 +0200 | [diff] [blame] | 24 | select SOC_AMD_COMMON_BLOCK_ACPIMMIO_PM_IO_ACCESS |
Felix Held | c07c7c9 | 2020-12-04 18:50:53 +0100 | [diff] [blame] | 25 | select SOC_AMD_COMMON_BLOCK_AOAC |
| 26 | select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS |
| 27 | select SOC_AMD_COMMON_BLOCK_CAR |
Felix Held | 96fd62f | 2023-03-24 16:55:50 +0100 | [diff] [blame] | 28 | select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H |
CoolStar | 835af76 | 2023-10-17 00:30:19 -0700 | [diff] [blame] | 29 | select SOC_AMD_COMMON_BLOCK_GRAPHICS |
Felix Held | c07c7c9 | 2020-12-04 18:50:53 +0100 | [diff] [blame] | 30 | select SOC_AMD_COMMON_BLOCK_HDA |
Karthikeyan Ramasubramanian | 0dbea48 | 2021-03-08 23:23:50 -0700 | [diff] [blame] | 31 | select SOC_AMD_COMMON_BLOCK_I2C |
Felix Held | c07c7c9 | 2020-12-04 18:50:53 +0100 | [diff] [blame] | 32 | select SOC_AMD_COMMON_BLOCK_IOMMU |
| 33 | select SOC_AMD_COMMON_BLOCK_LPC |
Felix Held | 1e1d490 | 2021-07-14 00:05:39 +0200 | [diff] [blame] | 34 | select SOC_AMD_COMMON_BLOCK_MCA |
Felix Held | c07c7c9 | 2020-12-04 18:50:53 +0100 | [diff] [blame] | 35 | select SOC_AMD_COMMON_BLOCK_PCI |
Felix Held | c0538d4 | 2021-04-13 19:56:10 +0200 | [diff] [blame] | 36 | select SOC_AMD_COMMON_BLOCK_PM |
Felix Held | c07c7c9 | 2020-12-04 18:50:53 +0100 | [diff] [blame] | 37 | select SOC_AMD_COMMON_BLOCK_PSP_GEN1 |
Felix Held | c07c7c9 | 2020-12-04 18:50:53 +0100 | [diff] [blame] | 38 | select SOC_AMD_COMMON_BLOCK_SATA |
| 39 | select SOC_AMD_COMMON_BLOCK_SMBUS |
| 40 | select SOC_AMD_COMMON_BLOCK_SMI |
Felix Held | bc13481 | 2021-02-10 02:26:10 +0100 | [diff] [blame] | 41 | select SOC_AMD_COMMON_BLOCK_SMM |
Felix Held | 7d8c832 | 2023-03-25 04:59:18 +0100 | [diff] [blame] | 42 | select SOC_AMD_COMMON_BLOCK_SMN |
Felix Held | c07c7c9 | 2020-12-04 18:50:53 +0100 | [diff] [blame] | 43 | select SOC_AMD_COMMON_BLOCK_SPI |
Felix Held | a3391e5 | 2023-03-24 00:20:02 +0100 | [diff] [blame] | 44 | select SOC_AMD_COMMON_BLOCK_SVI2 |
Felix Held | 91ef925 | 2021-01-12 23:44:05 +0100 | [diff] [blame] | 45 | select SOC_AMD_COMMON_BLOCK_UART |
Matt DeVillier | 1e0842e | 2023-10-24 11:43:25 -0500 | [diff] [blame] | 46 | select SOC_AMD_COMMON_LATE_SMM_LOCKING |
Felix Held | c07c7c9 | 2020-12-04 18:50:53 +0100 | [diff] [blame] | 47 | select SSE2 |
| 48 | select TSC_SYNC_LFENCE |
Martin Roth | bcb610a | 2022-10-29 13:31:54 -0600 | [diff] [blame] | 49 | select USE_DDR4 |
Felix Held | c07c7c9 | 2020-12-04 18:50:53 +0100 | [diff] [blame] | 50 | select X86_AMD_FIXED_MTRRS |
Elyes Haouas | 3cd06cc | 2023-01-05 07:42:24 +0100 | [diff] [blame] | 51 | help |
| 52 | AMD support for SOCs in Family 15h Models 60h-6Fh and Models 70h-7Fh. |
| 53 | |
| 54 | if SOC_AMD_STONEYRIDGE |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 55 | |
Marshall Dawson | 12294d0 | 2019-11-25 07:21:18 -0700 | [diff] [blame] | 56 | config AMD_APU_STONEYRIDGE |
| 57 | bool |
| 58 | help |
| 59 | AMD Stoney Ridge APU |
| 60 | |
Marshall Dawson | e1988f5 | 2019-11-25 11:15:35 -0700 | [diff] [blame] | 61 | config AMD_APU_PRAIRIEFALCON |
| 62 | bool |
| 63 | help |
| 64 | AMD Embedded Prairie Falcon APU |
| 65 | |
Marshall Dawson | 12294d0 | 2019-11-25 07:21:18 -0700 | [diff] [blame] | 66 | config AMD_APU_MERLINFALCON |
| 67 | bool |
| 68 | help |
Marshall Dawson | e1988f5 | 2019-11-25 11:15:35 -0700 | [diff] [blame] | 69 | AMD Embedded Merlin Falcon APU |
Marshall Dawson | 12294d0 | 2019-11-25 07:21:18 -0700 | [diff] [blame] | 70 | |
Marshall Dawson | 3ac0ab5 | 2019-11-24 19:03:56 -0700 | [diff] [blame] | 71 | config AMD_APU_PKG_FP4 |
| 72 | bool |
| 73 | help |
| 74 | AMD FP4 package |
| 75 | |
| 76 | config AMD_APU_PKG_FT4 |
| 77 | bool |
| 78 | help |
| 79 | AMD FT4 package |
| 80 | |
| 81 | config AMD_SOC_PACKAGE |
| 82 | string |
| 83 | default "FP4" if AMD_APU_PKG_FP4 |
| 84 | default "FT4" if AMD_APU_PKG_FT4 |
| 85 | |
Felix Held | b68e224 | 2022-10-12 18:44:06 +0200 | [diff] [blame] | 86 | config CHIPSET_DEVICETREE |
| 87 | string |
| 88 | default "soc/amd/stoneyridge/chipset_cz.cb" if AMD_APU_MERLINFALCON |
| 89 | default "soc/amd/stoneyridge/chipset_st.cb" if AMD_APU_PRAIRIEFALCON |
| 90 | default "soc/amd/stoneyridge/chipset_st.cb" if AMD_APU_STONEYRIDGE |
| 91 | |
Marshall Dawson | e7557de | 2017-06-09 16:35:14 -0600 | [diff] [blame] | 92 | config VBOOT |
Marshall Dawson | e7557de | 2017-06-09 16:35:14 -0600 | [diff] [blame] | 93 | select VBOOT_STARTS_IN_BOOTBLOCK |
Marc Jones | 4c887ea | 2018-04-25 16:43:18 -0600 | [diff] [blame] | 94 | select VBOOT_VBNV_CMOS |
| 95 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
Marshall Dawson | e7557de | 2017-06-09 16:35:14 -0600 | [diff] [blame] | 96 | |
Marc Jones | 21cde8b | 2017-05-07 16:47:36 -0600 | [diff] [blame] | 97 | # TODO: Sync these with definitions in PI vendorcode. |
| 98 | # DCACHE_RAM_BASE must equal BSP_STACK_BASE_ADDR. |
| 99 | # DCACHE_RAM_SIZE must equal BSP_STACK_SIZE. |
| 100 | |
| 101 | config DCACHE_RAM_BASE |
| 102 | hex |
| 103 | default 0x30000 |
| 104 | |
| 105 | config DCACHE_RAM_SIZE |
| 106 | hex |
| 107 | default 0x10000 |
| 108 | |
Jeremy Compostella | 052fb7c | 2023-08-18 14:25:22 -0700 | [diff] [blame] | 109 | config PRERAM_CBFS_CACHE_SIZE |
| 110 | default 0x0 |
| 111 | |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 112 | config DCACHE_BSP_STACK_SIZE |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 113 | hex |
| 114 | default 0x4000 |
| 115 | help |
| 116 | The amount of anticipated stack usage in CAR by bootblock and |
| 117 | other stages. |
| 118 | |
Marshall Dawson | 7c3f1e7 | 2017-08-24 09:59:10 -0600 | [diff] [blame] | 119 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 120 | hex |
Marshall Dawson | 1df6bc6 | 2017-12-19 20:41:29 -0700 | [diff] [blame] | 121 | default 0x1600 |
Marshall Dawson | 7c3f1e7 | 2017-08-24 09:59:10 -0600 | [diff] [blame] | 122 | help |
| 123 | Increase this value if preram cbmem console is getting truncated |
| 124 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 125 | config BOTTOMIO_POSITION |
| 126 | hex "Bottom of 32-bit IO space" |
| 127 | default 0xD0000000 |
| 128 | help |
| 129 | If PCI peripherals with big BARs are connected to the system |
| 130 | the bottom of the IO must be decreased to allocate such |
| 131 | devices. |
| 132 | |
| 133 | Declare the beginning of the 128MB-aligned MMIO region. This |
| 134 | option is useful when PCI peripherals requesting large address |
| 135 | ranges are present. |
| 136 | |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 137 | config ECAM_MMCONF_BASE_ADDRESS |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 138 | default 0xF8000000 |
| 139 | |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 140 | config ECAM_MMCONF_BUS_NUMBER |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 141 | default 64 |
| 142 | |
Nico Huber | 2c5f24e | 2024-01-25 19:48:17 +0100 | [diff] [blame] | 143 | # This number must be equal or lower than what's reported in ACPI PCI _CRS |
| 144 | config DOMAIN_RESOURCE_32BIT_LIMIT |
| 145 | default ECAM_MMCONF_BASE_ADDRESS |
| 146 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 147 | config VGA_BIOS_ID |
| 148 | string |
Felix Held | 0b03c08 | 2023-03-24 22:49:48 +0100 | [diff] [blame] | 149 | default "1002,9870" if AMD_APU_MERLINFALCON |
| 150 | default "1002,98e0" |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 151 | help |
| 152 | The default VGA BIOS PCI vendor/device ID should be set to the |
| 153 | result of the map_oprom_vendev() function in northbridge.c. |
| 154 | |
| 155 | config VGA_BIOS_FILE |
| 156 | string |
Marshall Dawson | 7987c1c | 2019-11-25 08:29:28 -0700 | [diff] [blame] | 157 | default "3rdparty/amd_blobs/stoneyridge/CarrizoGenericVbios.bin" if AMD_APU_MERLINFALCON |
Marshall Dawson | e1988f5 | 2019-11-25 11:15:35 -0700 | [diff] [blame] | 158 | default "3rdparty/amd_blobs/stoneyridge/StoneyGenericVbios.bin" if AMD_APU_PRAIRIEFALCON |
| 159 | default "3rdparty/amd_blobs/stoneyridge/StoneyGenericVbios.bin" if AMD_APU_STONEYRIDGE |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 160 | |
Marshall Dawson | 668dea0 | 2017-11-29 09:57:15 -0700 | [diff] [blame] | 161 | config S3_VGA_ROM_RUN |
| 162 | bool |
| 163 | default n |
| 164 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 165 | config EHCI_BAR |
| 166 | hex |
| 167 | default 0xfef00000 |
| 168 | |
| 169 | config STONEYRIDGE_XHCI_ENABLE |
| 170 | bool "Enable Stoney Ridge XHCI Controller" |
| 171 | default y |
| 172 | help |
| 173 | The XHCI controller must be enabled and the XHCI firmware |
| 174 | must be added in order to have USB 3.0 support configured |
| 175 | by coreboot. The OS will be responsible for enabling the XHCI |
Jonathan Neuschäfer | 45e6c82 | 2018-12-11 17:53:07 +0100 | [diff] [blame] | 176 | controller if the XHCI firmware is available but the |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 177 | XHCI controller is not enabled by coreboot. |
| 178 | |
| 179 | config STONEYRIDGE_XHCI_FWM |
| 180 | bool "Add xhci firmware" |
| 181 | default y |
| 182 | help |
| 183 | Add Stoney Ridge XHCI Firmware to support the onboard USB 3.0 |
| 184 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 185 | config STONEYRIDGE_GEC_FWM |
| 186 | bool |
| 187 | default n |
| 188 | help |
| 189 | Add Stoney Ridge GEC Firmware to support the onboard gigabit Ethernet MAC. |
| 190 | Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard. |
| 191 | |
| 192 | config STONEYRIDGE_XHCI_FWM_FILE |
| 193 | string "XHCI firmware path and filename" |
Marshall Dawson | 7987c1c | 2019-11-25 08:29:28 -0700 | [diff] [blame] | 194 | default "3rdparty/amd_blobs/stoneyridge/xhci.bin" |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 195 | depends on STONEYRIDGE_XHCI_FWM |
| 196 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 197 | config STONEYRIDGE_GEC_FWM_FILE |
| 198 | string "GEC firmware path and filename" |
| 199 | depends on STONEYRIDGE_GEC_FWM |
| 200 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 201 | config AMDFW_CONFIG_FILE |
| 202 | string |
| 203 | string "AMD PSP Firmware config file" |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 204 | default "src/soc/amd/stoneyridge/fw_cz.cfg" if AMD_APU_MERLINFALCON |
| 205 | default "src/soc/amd/stoneyridge/fw_st.cfg" if AMD_APU_PRAIRIEFALCON |
| 206 | default "src/soc/amd/stoneyridge/fw_st.cfg" if AMD_APU_STONEYRIDGE |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 207 | |
| 208 | config STONEYRIDGE_SATA_MODE |
| 209 | int "SATA Mode" |
| 210 | default 0 |
| 211 | range 0 6 |
| 212 | help |
| 213 | Select the mode in which SATA should be driven. |
| 214 | The default is NATIVE. |
| 215 | 0: NATIVE mode does not require a ROM. |
| 216 | 2: AHCI may work with or without AHCI ROM. It depends on the payload support. |
| 217 | For example, seabios does not require the AHCI ROM. |
| 218 | 3: LEGACY IDE |
| 219 | 4: IDE to AHCI |
| 220 | 5: AHCI7804: ROM Required, and AMD driver required in the OS. |
| 221 | 6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS. |
| 222 | |
| 223 | comment "NATIVE" |
| 224 | depends on STONEYRIDGE_SATA_MODE = 0 |
| 225 | |
| 226 | comment "AHCI" |
| 227 | depends on STONEYRIDGE_SATA_MODE = 2 |
| 228 | |
| 229 | comment "LEGACY IDE" |
| 230 | depends on STONEYRIDGE_SATA_MODE = 3 |
| 231 | |
| 232 | comment "IDE to AHCI" |
| 233 | depends on STONEYRIDGE_SATA_MODE = 4 |
| 234 | |
| 235 | comment "AHCI7804" |
| 236 | depends on STONEYRIDGE_SATA_MODE = 5 |
| 237 | |
| 238 | comment "IDE to AHCI7804" |
| 239 | depends on STONEYRIDGE_SATA_MODE = 6 |
| 240 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 241 | config STONEYRIDGE_LEGACY_FREE |
| 242 | bool "System is legacy free" |
| 243 | help |
| 244 | Select y if there is no keyboard controller in the system. |
| 245 | This sets variables in AGESA and ACPI. |
| 246 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 247 | config SERIRQ_CONTINUOUS_MODE |
| 248 | bool |
| 249 | default n |
| 250 | help |
| 251 | Set this option to y for serial IRQ in continuous mode. |
| 252 | Otherwise it is in quiet mode. |
| 253 | |
Arthur Heymans | b5e72b6 | 2018-01-02 23:41:24 +0100 | [diff] [blame] | 254 | config CONSOLE_UART_BASE_ADDRESS |
| 255 | depends on CONSOLE_SERIAL |
| 256 | hex |
| 257 | default 0xfedc6000 |
| 258 | |
Marshall Dawson | c6ef9db | 2017-05-14 14:16:56 -0600 | [diff] [blame] | 259 | config SMM_TSEG_SIZE |
| 260 | hex |
Felix Held | e22eef7 | 2021-02-10 22:22:07 +0100 | [diff] [blame] | 261 | default 0x800000 if HAVE_SMI_HANDLER |
Marshall Dawson | c6ef9db | 2017-05-14 14:16:56 -0600 | [diff] [blame] | 262 | default 0x0 |
| 263 | |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 264 | config SMM_RESERVED_SIZE |
| 265 | hex |
Zheng Bao | 2d2c27e | 2022-11-18 15:01:22 +0800 | [diff] [blame] | 266 | default 0x160000 |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 267 | |
Raul E Rangel | 846b494 | 2018-06-12 10:43:09 -0600 | [diff] [blame] | 268 | config SMM_MODULE_STACK_SIZE |
| 269 | hex |
| 270 | default 0x800 |
| 271 | |
Marc Jones | e013df9 | 2017-08-23 16:28:02 -0600 | [diff] [blame] | 272 | config ACPI_CPU_STRING |
| 273 | string |
Felix Held | 3cf05b5 | 2023-05-15 19:16:22 +0200 | [diff] [blame] | 274 | default "P%03X" |
Marc Jones | e013df9 | 2017-08-23 16:28:02 -0600 | [diff] [blame] | 275 | |
Felix Held | fc709fe | 2023-03-24 21:41:35 +0100 | [diff] [blame] | 276 | config ACPI_SSDT_PSD_INDEPENDENT |
| 277 | default n |
| 278 | |
Marshall Dawson | 9a32c41 | 2018-09-04 13:29:12 -0600 | [diff] [blame] | 279 | config ACPI_BERT |
| 280 | bool "Build ACPI BERT Table" |
| 281 | default y |
| 282 | depends on HAVE_ACPI_TABLES |
| 283 | help |
| 284 | Report Machine Check errors identified in POST to the OS in an |
| 285 | ACPI Boot Error Record Table. This option reserves an 8MB region |
| 286 | for building the error structures. |
| 287 | |
Marshall Dawson | 25eb2bc | 2019-03-14 12:42:46 -0600 | [diff] [blame] | 288 | config USE_PSPSECUREOS |
Martin Roth | b617e32 | 2017-09-07 13:23:55 -0600 | [diff] [blame] | 289 | bool "Include PSP SecureOS blobs in AMD firmware" |
| 290 | default y |
| 291 | help |
| 292 | Include the PspSecureOs, PspTrustlet and TrustletKey binaries |
| 293 | in the amdfw section. |
| 294 | |
| 295 | If unsure, answer 'y' |
| 296 | |
Richard Spiegel | 1bc578a | 2019-06-18 18:19:47 -0700 | [diff] [blame] | 297 | config SOC_AMD_PSP_SELECTABLE_SMU_FW |
| 298 | bool |
Marshall Dawson | 12294d0 | 2019-11-25 07:21:18 -0700 | [diff] [blame] | 299 | default y if AMD_APU_STONEYRIDGE |
Richard Spiegel | 1bc578a | 2019-06-18 18:19:47 -0700 | [diff] [blame] | 300 | help |
| 301 | Some ST implementations allow storing SMU firmware into cbfs and |
| 302 | calling the PSP to load the blobs at the proper time. |
| 303 | |
| 304 | Merlin Falcon does not support it. If you are using 00670F00 SOC, |
| 305 | ask your AMD representative if it supports it or not. |
| 306 | |
Marshall Dawson | 5f0520a | 2017-10-30 16:11:45 -0600 | [diff] [blame] | 307 | config SOC_AMD_SMU_FANLESS |
| 308 | bool |
| 309 | depends on SOC_AMD_PSP_SELECTABLE_SMU_FW |
| 310 | default n if SOC_AMD_SMU_NOTFANLESS |
| 311 | default y |
| 312 | |
| 313 | config SOC_AMD_SMU_FANNED |
| 314 | bool |
| 315 | depends on SOC_AMD_PSP_SELECTABLE_SMU_FW |
| 316 | default n |
| 317 | select SOC_AMD_SMU_NOTFANLESS |
| 318 | |
| 319 | config SOC_AMD_SMU_NOTFANLESS # helper symbol - do not use |
| 320 | bool |
| 321 | depends on SOC_AMD_PSP_SELECTABLE_SMU_FW |
| 322 | |
Martin Roth | 30f9b95 | 2017-10-03 15:54:45 -0600 | [diff] [blame] | 323 | config AMDFW_OUTSIDE_CBFS |
| 324 | bool "The AMD firmware is outside CBFS" |
| 325 | default n |
| 326 | help |
| 327 | The AMDFW (PSP) is typically locatable in cbfs. Select this |
| 328 | option to manually attach the generated amdfw.rom outside of |
| 329 | cbfs. The location is selected by the FWM position. |
| 330 | |
Marc Jones | 17431ab | 2017-11-16 15:26:00 -0700 | [diff] [blame] | 331 | config DIMM_SPD_SIZE |
Marc Jones | 17431ab | 2017-11-16 15:26:00 -0700 | [diff] [blame] | 332 | default 512 # DDR4 |
| 333 | |
Marc Jones | 578a79d | 2017-12-06 16:27:04 -0700 | [diff] [blame] | 334 | config RO_REGION_ONLY |
| 335 | string |
Matt DeVillier | 1e54a18 | 2022-10-04 16:34:21 -0500 | [diff] [blame] | 336 | depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A |
Marc Jones | 578a79d | 2017-12-06 16:27:04 -0700 | [diff] [blame] | 337 | default "apu/amdfw" |
| 338 | |
Chris Ching | 6fc39d4 | 2017-12-20 16:06:03 -0700 | [diff] [blame] | 339 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 340 | int |
| 341 | default 133 |
| 342 | |
Felix Held | 27b295b | 2021-03-25 01:20:41 +0100 | [diff] [blame] | 343 | config DISABLE_KEYBOARD_RESET_PIN |
| 344 | bool |
| 345 | help |
| 346 | Instruct the SoC to not use the state of GPIO_129 as keyboard reset |
| 347 | signal. When this pin is used as GPIO and the keyboard reset |
| 348 | functionality isn't disabled, configuring it as an output and driving |
| 349 | it as 0 will cause a reset. |
| 350 | |
Arthur Heymans | dd7ec09 | 2022-05-23 16:06:06 +0200 | [diff] [blame] | 351 | config ACPI_BERT_SIZE |
| 352 | hex |
| 353 | default 0x100000 if ACPI_BERT |
| 354 | default 0x0 |
| 355 | help |
| 356 | Specify the amount of DRAM reserved for gathering the data used to |
| 357 | generate the ACPI table. |
| 358 | |
Marshall Dawson | 6851922 | 2019-11-25 11:36:15 -0700 | [diff] [blame] | 359 | endif # SOC_AMD_STONEYRIDGE |