soc/amd/stoneyridge: use SOC_AMD_COMMON_BLOCK_UART
Since the functions that get called by the coreboot console
initialization code aren't in the SOC-specific code anymore, the SOC's
uart.c can be included unconditionally in the build now. This also
replaces the STONEYRIDGE_UART Kconfig option with the common
AMD_SOC_CONSOLE_UART one.
Change-Id: I09c15566a402895d6388715e8e5a802dc3c94fdd
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49375
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index 206c95a..6aebd85 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -42,6 +42,7 @@
select SOC_AMD_COMMON_BLOCK_SMBUS
select SOC_AMD_COMMON_BLOCK_SMI
select SOC_AMD_COMMON_BLOCK_SPI
+ select SOC_AMD_COMMON_BLOCK_UART
select SSE2
select TSC_SYNC_LFENCE
select X86_AMD_FIXED_MTRRS
@@ -258,20 +259,6 @@
Base address for the ACPI registers.
This value must match the hardcoded value of AGESA.
-config STONEYRIDGE_UART
- bool "UART controller on Stoney Ridge"
- default n
- select DRIVERS_UART_8250MEM
- select DRIVERS_UART_8250MEM_32
- select NO_UART_ON_SUPERIO
- select UART_OVERRIDE_REFCLK
- help
- There are two UART controllers in Stoney Ridge.
- The UART registers are memory-mapped. UART
- controller 0 registers range from FEDC_6000h
- to FEDC_6FFFh. UART controller 1 registers
- range from FEDC_8000h to FEDC_8FFFh.
-
config CONSOLE_UART_BASE_ADDRESS
depends on CONSOLE_SERIAL
hex