soc/amd/stoneyridge/cpu: implement get_pstate_latency
Both the algorithm and the registers involved are described in the
public version of BKDG #55072 Rev 3.09 in chapter 2.5.2.1.7.3.2 _PSS
(Performance Supported States).
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9b2c177d9d80c5c205340f3f428186d6b8eb7e98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index 0d790a3..6f5c6e0 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -39,6 +39,7 @@
select SOC_AMD_COMMON_BLOCK_SMBUS
select SOC_AMD_COMMON_BLOCK_SMI
select SOC_AMD_COMMON_BLOCK_SMM
+ select SOC_AMD_COMMON_BLOCK_SMN
select SOC_AMD_COMMON_BLOCK_SPI
select SOC_AMD_COMMON_BLOCK_SVI2
select SOC_AMD_COMMON_BLOCK_UART