Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2017 Advanced Micro Devices, Inc. |
| 5 | ## |
| 6 | ## This program is free software; you can redistribute it and/or modify |
| 7 | ## it under the terms of the GNU General Public License as published by |
| 8 | ## the Free Software Foundation; version 2 of the License. |
| 9 | ## |
| 10 | ## This program is distributed in the hope that it will be useful, |
| 11 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | ## GNU General Public License for more details. |
| 14 | ## |
| 15 | |
Marc Jones | 21cde8b | 2017-05-07 16:47:36 -0600 | [diff] [blame] | 16 | config SOC_AMD_STONEYRIDGE_FP4 |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 17 | bool |
Marshall Dawson | 3ac0ab5 | 2019-11-24 19:03:56 -0700 | [diff] [blame^] | 18 | select AMD_APU_PKG_FP4 |
Marc Jones | 21cde8b | 2017-05-07 16:47:36 -0600 | [diff] [blame] | 19 | help |
| 20 | AMD Stoney Ridge FP4 support |
| 21 | |
| 22 | config SOC_AMD_STONEYRIDGE_FT4 |
| 23 | bool |
Marshall Dawson | 3ac0ab5 | 2019-11-24 19:03:56 -0700 | [diff] [blame^] | 24 | select AMD_APU_PKG_FT4 |
Marc Jones | 21cde8b | 2017-05-07 16:47:36 -0600 | [diff] [blame] | 25 | help |
| 26 | AMD Stoney Ridge FT4 support |
| 27 | |
Richard Spiegel | 1bc578a | 2019-06-18 18:19:47 -0700 | [diff] [blame] | 28 | config SOC_AMD_MERLINFALCON |
| 29 | bool |
Marshall Dawson | 3ac0ab5 | 2019-11-24 19:03:56 -0700 | [diff] [blame^] | 30 | select AMD_APU_PKG_FP4 |
Richard Spiegel | 1bc578a | 2019-06-18 18:19:47 -0700 | [diff] [blame] | 31 | help |
| 32 | AMD Merlin Falcon FP4 support |
| 33 | |
| 34 | config HAVE_MERLINFALCON_BINARIES |
| 35 | depends on SOC_AMD_MERLINFALCON |
| 36 | bool "Merlinfalcon binaries are present" |
| 37 | default n |
| 38 | help |
| 39 | This config option will be removed once the binaries are merged |
| 40 | to the blobs repo. See 33615. |
| 41 | |
| 42 | if SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_MERLINFALCON |
Marc Jones | 21cde8b | 2017-05-07 16:47:36 -0600 | [diff] [blame] | 43 | |
| 44 | config CPU_SPECIFIC_OPTIONS |
| 45 | def_bool y |
| 46 | select ARCH_BOOTBLOCK_X86_32 |
| 47 | select ARCH_VERSTAGE_X86_32 |
| 48 | select ARCH_ROMSTAGE_X86_32 |
| 49 | select ARCH_RAMSTAGE_X86_32 |
Marshall Dawson | 82145a1 | 2017-10-20 12:36:35 -0600 | [diff] [blame] | 50 | select X86_AMD_FIXED_MTRRS |
Marshall Dawson | 68592c3 | 2017-11-06 10:56:52 -0700 | [diff] [blame] | 51 | select ACPI_AMD_HARDWARE_SLEEP_VALUES |
Aaron Durbin | 51e4c1a | 2018-01-24 17:42:51 -0700 | [diff] [blame] | 52 | select COLLECT_TIMESTAMPS_NO_TSC |
Chris Ching | 6fc39d4 | 2017-12-20 16:06:03 -0700 | [diff] [blame] | 53 | select DRIVERS_I2C_DESIGNWARE |
Marc Jones | 9156cac | 2017-07-12 11:05:38 -0600 | [diff] [blame] | 54 | select GENERIC_GPIO_LIB |
Aaron Durbin | 51e4c1a | 2018-01-24 17:42:51 -0700 | [diff] [blame] | 55 | select GENERIC_UDELAY |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 56 | select IOAPIC |
| 57 | select HAVE_USBDEBUG_OPTIONS |
Richard Spiegel | bf17124 | 2019-08-21 10:09:51 -0700 | [diff] [blame] | 58 | select SOC_AMD_COMMON_BLOCK_SPI |
Marc Jones | 21cde8b | 2017-05-07 16:47:36 -0600 | [diff] [blame] | 59 | select TSC_SYNC_LFENCE |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 60 | select SOC_AMD_PI |
Marshall Dawson | 68243a5 | 2017-06-15 16:59:20 -0600 | [diff] [blame] | 61 | select SOC_AMD_COMMON |
| 62 | select SOC_AMD_COMMON_BLOCK |
Marshall Dawson | ec63a71 | 2019-05-03 12:55:16 -0600 | [diff] [blame] | 63 | select SOC_AMD_COMMON_BLOCK_IOMMU |
Marshall Dawson | 69486ca | 2019-05-02 12:03:45 -0600 | [diff] [blame] | 64 | select SOC_AMD_COMMON_BLOCK_ACPIMMIO |
Marshall Dawson | 251d305 | 2019-05-02 17:27:57 -0600 | [diff] [blame] | 65 | select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS |
Marshall Dawson | 3ce0360 | 2019-05-03 10:20:44 -0600 | [diff] [blame] | 66 | select SOC_AMD_COMMON_BLOCK_ACPI |
Marshall Dawson | 6ab5ed3 | 2019-05-29 09:24:18 -0600 | [diff] [blame] | 67 | select SOC_AMD_COMMON_BLOCK_LPC |
Richard Spiegel | 2bbc3dc | 2017-12-06 16:14:58 -0700 | [diff] [blame] | 68 | select SOC_AMD_COMMON_BLOCK_PCI |
Marshall Dawson | 43c26cb | 2019-05-03 12:42:29 -0600 | [diff] [blame] | 69 | select SOC_AMD_COMMON_BLOCK_HDA |
Marshall Dawson | aa67def | 2019-05-03 16:10:34 -0600 | [diff] [blame] | 70 | select SOC_AMD_COMMON_BLOCK_SATA |
Richard Spiegel | 19f67a3 | 2017-12-08 18:16:02 -0700 | [diff] [blame] | 71 | select SOC_AMD_COMMON_BLOCK_PI |
Marshall Dawson | 68243a5 | 2017-06-15 16:59:20 -0600 | [diff] [blame] | 72 | select SOC_AMD_COMMON_BLOCK_PSP |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 73 | select SOC_AMD_COMMON_BLOCK_CAR |
Kyösti Mälkki | a8eb477 | 2018-06-28 17:23:27 +0300 | [diff] [blame] | 74 | select SOC_AMD_COMMON_BLOCK_S3 |
John E. Kabat Jr | af32770 | 2017-11-29 18:49:37 -0700 | [diff] [blame] | 75 | select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH |
Marc Jones | 4c887ea | 2018-04-25 16:43:18 -0600 | [diff] [blame] | 76 | select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 77 | select PARALLEL_MP |
Marc Jones | 33eef13 | 2017-10-26 16:50:42 -0600 | [diff] [blame] | 78 | select PARALLEL_MP_AP_WORK |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 79 | select HAVE_SMI_HANDLER |
Martin Roth | 37b8bde | 2017-09-26 09:41:10 -0600 | [diff] [blame] | 80 | select SSE2 |
Marc Jones | 17e85ad | 2017-12-20 16:21:25 -0700 | [diff] [blame] | 81 | select RTC |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 82 | |
Marshall Dawson | 3ac0ab5 | 2019-11-24 19:03:56 -0700 | [diff] [blame^] | 83 | config AMD_APU_PKG_FP4 |
| 84 | bool |
| 85 | help |
| 86 | AMD FP4 package |
| 87 | |
| 88 | config AMD_APU_PKG_FT4 |
| 89 | bool |
| 90 | help |
| 91 | AMD FT4 package |
| 92 | |
| 93 | config AMD_SOC_PACKAGE |
| 94 | string |
| 95 | default "FP4" if AMD_APU_PKG_FP4 |
| 96 | default "FT4" if AMD_APU_PKG_FT4 |
| 97 | |
Marshall Dawson | e7557de | 2017-06-09 16:35:14 -0600 | [diff] [blame] | 98 | config VBOOT |
Marshall Dawson | e7557de | 2017-06-09 16:35:14 -0600 | [diff] [blame] | 99 | select VBOOT_SEPARATE_VERSTAGE |
| 100 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 101 | select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT |
Marc Jones | 4c887ea | 2018-04-25 16:43:18 -0600 | [diff] [blame] | 102 | select VBOOT_VBNV_CMOS |
| 103 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
Marshall Dawson | e7557de | 2017-06-09 16:35:14 -0600 | [diff] [blame] | 104 | |
Marc Jones | 21cde8b | 2017-05-07 16:47:36 -0600 | [diff] [blame] | 105 | # TODO: Sync these with definitions in PI vendorcode. |
| 106 | # DCACHE_RAM_BASE must equal BSP_STACK_BASE_ADDR. |
| 107 | # DCACHE_RAM_SIZE must equal BSP_STACK_SIZE. |
| 108 | |
| 109 | config DCACHE_RAM_BASE |
| 110 | hex |
| 111 | default 0x30000 |
| 112 | |
| 113 | config DCACHE_RAM_SIZE |
| 114 | hex |
| 115 | default 0x10000 |
| 116 | |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 117 | config DCACHE_BSP_STACK_SIZE |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 118 | hex |
| 119 | default 0x4000 |
| 120 | help |
| 121 | The amount of anticipated stack usage in CAR by bootblock and |
| 122 | other stages. |
| 123 | |
Marshall Dawson | 7c3f1e7 | 2017-08-24 09:59:10 -0600 | [diff] [blame] | 124 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 125 | hex |
Marshall Dawson | 1df6bc6 | 2017-12-19 20:41:29 -0700 | [diff] [blame] | 126 | default 0x1600 |
Marshall Dawson | 7c3f1e7 | 2017-08-24 09:59:10 -0600 | [diff] [blame] | 127 | help |
| 128 | Increase this value if preram cbmem console is getting truncated |
| 129 | |
Marc Jones | 21cde8b | 2017-05-07 16:47:36 -0600 | [diff] [blame] | 130 | config CPU_ADDR_BITS |
| 131 | int |
| 132 | default 48 |
| 133 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 134 | config BOTTOMIO_POSITION |
| 135 | hex "Bottom of 32-bit IO space" |
| 136 | default 0xD0000000 |
| 137 | help |
| 138 | If PCI peripherals with big BARs are connected to the system |
| 139 | the bottom of the IO must be decreased to allocate such |
| 140 | devices. |
| 141 | |
| 142 | Declare the beginning of the 128MB-aligned MMIO region. This |
| 143 | option is useful when PCI peripherals requesting large address |
| 144 | ranges are present. |
| 145 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 146 | config MMCONF_BASE_ADDRESS |
| 147 | hex |
| 148 | default 0xF8000000 |
| 149 | |
| 150 | config MMCONF_BUS_NUMBER |
| 151 | int |
| 152 | default 64 |
| 153 | |
| 154 | config VGA_BIOS_ID |
| 155 | string |
Richard Spiegel | 1bc578a | 2019-06-18 18:19:47 -0700 | [diff] [blame] | 156 | default "1002,9874" if SOC_AMD_MERLINFALCON |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 157 | default "1002,98e4" |
| 158 | help |
| 159 | The default VGA BIOS PCI vendor/device ID should be set to the |
| 160 | result of the map_oprom_vendev() function in northbridge.c. |
| 161 | |
| 162 | config VGA_BIOS_FILE |
| 163 | string |
Richard Spiegel | 1bc578a | 2019-06-18 18:19:47 -0700 | [diff] [blame] | 164 | default "3rdparty/blobs/soc/amd/merlinfalcon/VBIOS.bin" if SOC_AMD_MERLINFALCON && HAVE_MERLINFALCON_BINARIES |
Richard Spiegel | 4eaf0fa | 2018-01-23 15:51:57 -0700 | [diff] [blame] | 165 | default "3rdparty/blobs/soc/amd/stoneyridge/VBIOS.bin" |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 166 | |
Marshall Dawson | 668dea0 | 2017-11-29 09:57:15 -0700 | [diff] [blame] | 167 | config S3_VGA_ROM_RUN |
| 168 | bool |
| 169 | default n |
| 170 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 171 | config HEAP_SIZE |
| 172 | hex |
| 173 | default 0xc0000 |
| 174 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 175 | config EHCI_BAR |
| 176 | hex |
| 177 | default 0xfef00000 |
| 178 | |
| 179 | config STONEYRIDGE_XHCI_ENABLE |
| 180 | bool "Enable Stoney Ridge XHCI Controller" |
| 181 | default y |
| 182 | help |
| 183 | The XHCI controller must be enabled and the XHCI firmware |
| 184 | must be added in order to have USB 3.0 support configured |
| 185 | by coreboot. The OS will be responsible for enabling the XHCI |
Jonathan Neuschäfer | 45e6c82 | 2018-12-11 17:53:07 +0100 | [diff] [blame] | 186 | controller if the XHCI firmware is available but the |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 187 | XHCI controller is not enabled by coreboot. |
| 188 | |
| 189 | config STONEYRIDGE_XHCI_FWM |
| 190 | bool "Add xhci firmware" |
| 191 | default y |
| 192 | help |
| 193 | Add Stoney Ridge XHCI Firmware to support the onboard USB 3.0 |
| 194 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 195 | config STONEYRIDGE_GEC_FWM |
| 196 | bool |
| 197 | default n |
| 198 | help |
| 199 | Add Stoney Ridge GEC Firmware to support the onboard gigabit Ethernet MAC. |
| 200 | Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard. |
| 201 | |
| 202 | config STONEYRIDGE_XHCI_FWM_FILE |
| 203 | string "XHCI firmware path and filename" |
Richard Spiegel | a987278 | 2018-01-04 17:26:54 -0700 | [diff] [blame] | 204 | default "3rdparty/blobs/soc/amd/stoneyridge/xhci.bin" |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 205 | depends on STONEYRIDGE_XHCI_FWM |
| 206 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 207 | config STONEYRIDGE_GEC_FWM_FILE |
| 208 | string "GEC firmware path and filename" |
| 209 | depends on STONEYRIDGE_GEC_FWM |
| 210 | |
| 211 | config AMD_PUBKEY_FILE |
| 212 | string "AMD public Key" |
Richard Spiegel | 1bc578a | 2019-06-18 18:19:47 -0700 | [diff] [blame] | 213 | default "3rdparty/blobs/soc/amd/merlinfalcon/PSP/AmdPubKeyCZ.bin" if SOC_AMD_MERLINFALCON && HAVE_MERLINFALCON_BINARIES |
Richard Spiegel | a987278 | 2018-01-04 17:26:54 -0700 | [diff] [blame] | 214 | default "3rdparty/blobs/soc/amd/stoneyridge/PSP/AmdPubKeyST.bin" |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 215 | |
| 216 | config STONEYRIDGE_SATA_MODE |
| 217 | int "SATA Mode" |
| 218 | default 0 |
| 219 | range 0 6 |
| 220 | help |
| 221 | Select the mode in which SATA should be driven. |
| 222 | The default is NATIVE. |
| 223 | 0: NATIVE mode does not require a ROM. |
| 224 | 2: AHCI may work with or without AHCI ROM. It depends on the payload support. |
| 225 | For example, seabios does not require the AHCI ROM. |
| 226 | 3: LEGACY IDE |
| 227 | 4: IDE to AHCI |
| 228 | 5: AHCI7804: ROM Required, and AMD driver required in the OS. |
| 229 | 6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS. |
| 230 | |
| 231 | comment "NATIVE" |
| 232 | depends on STONEYRIDGE_SATA_MODE = 0 |
| 233 | |
| 234 | comment "AHCI" |
| 235 | depends on STONEYRIDGE_SATA_MODE = 2 |
| 236 | |
| 237 | comment "LEGACY IDE" |
| 238 | depends on STONEYRIDGE_SATA_MODE = 3 |
| 239 | |
| 240 | comment "IDE to AHCI" |
| 241 | depends on STONEYRIDGE_SATA_MODE = 4 |
| 242 | |
| 243 | comment "AHCI7804" |
| 244 | depends on STONEYRIDGE_SATA_MODE = 5 |
| 245 | |
| 246 | comment "IDE to AHCI7804" |
| 247 | depends on STONEYRIDGE_SATA_MODE = 6 |
| 248 | |
| 249 | if STONEYRIDGE_SATA_MODE = 2 || STONEYRIDGE_SATA_MODE = 5 |
| 250 | |
| 251 | config AHCI_ROM_ID |
| 252 | string "AHCI device PCI IDs" |
| 253 | default "1022,7801" if STONEYRIDGE_SATA_MODE = 2 |
| 254 | default "1022,7804" if STONEYRIDGE_SATA_MODE = 5 |
| 255 | |
| 256 | endif # STONEYRIDGE_SATA_MODE = 2 || STONEYRIDGE_SATA_MODE = 5 |
| 257 | |
| 258 | config STONEYRIDGE_LEGACY_FREE |
| 259 | bool "System is legacy free" |
| 260 | help |
| 261 | Select y if there is no keyboard controller in the system. |
| 262 | This sets variables in AGESA and ACPI. |
| 263 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 264 | config SERIRQ_CONTINUOUS_MODE |
| 265 | bool |
| 266 | default n |
| 267 | help |
| 268 | Set this option to y for serial IRQ in continuous mode. |
| 269 | Otherwise it is in quiet mode. |
| 270 | |
| 271 | config STONEYRIDGE_ACPI_IO_BASE |
| 272 | hex |
| 273 | default 0x400 |
| 274 | help |
| 275 | Base address for the ACPI registers. |
| 276 | This value must match the hardcoded value of AGESA. |
| 277 | |
| 278 | config STONEYRIDGE_UART |
| 279 | bool "UART controller on Stoney Ridge" |
| 280 | default n |
| 281 | select DRIVERS_UART_8250MEM |
| 282 | select DRIVERS_UART_8250MEM_32 |
| 283 | select NO_UART_ON_SUPERIO |
| 284 | select UART_OVERRIDE_REFCLK |
| 285 | help |
| 286 | There are two UART controllers in Stoney Ridge. |
| 287 | The UART registers are memory-mapped. UART |
| 288 | controller 0 registers range from FEDC_6000h |
| 289 | to FEDC_6FFFh. UART controller 1 registers |
| 290 | range from FEDC_8000h to FEDC_8FFFh. |
| 291 | |
Arthur Heymans | b5e72b6 | 2018-01-02 23:41:24 +0100 | [diff] [blame] | 292 | config CONSOLE_UART_BASE_ADDRESS |
| 293 | depends on CONSOLE_SERIAL |
| 294 | hex |
| 295 | default 0xfedc6000 |
| 296 | |
Marshall Dawson | c6ef9db | 2017-05-14 14:16:56 -0600 | [diff] [blame] | 297 | config SMM_TSEG_SIZE |
| 298 | hex |
Marshall Dawson | 0801b33 | 2017-08-25 15:29:45 -0600 | [diff] [blame] | 299 | default 0x800000 if SMM_TSEG && HAVE_SMI_HANDLER |
Marshall Dawson | c6ef9db | 2017-05-14 14:16:56 -0600 | [diff] [blame] | 300 | default 0x0 |
| 301 | |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 302 | config SMM_RESERVED_SIZE |
| 303 | hex |
Marshall Dawson | fceac7e | 2018-05-18 14:40:53 -0600 | [diff] [blame] | 304 | default 0x150000 |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 305 | |
Raul E Rangel | 846b494 | 2018-06-12 10:43:09 -0600 | [diff] [blame] | 306 | config SMM_MODULE_STACK_SIZE |
| 307 | hex |
| 308 | default 0x800 |
| 309 | |
Marc Jones | e013df9 | 2017-08-23 16:28:02 -0600 | [diff] [blame] | 310 | config ACPI_CPU_STRING |
| 311 | string |
| 312 | default "\\_PR.P%03d" |
| 313 | |
Marshall Dawson | 9a32c41 | 2018-09-04 13:29:12 -0600 | [diff] [blame] | 314 | config ACPI_BERT |
| 315 | bool "Build ACPI BERT Table" |
| 316 | default y |
| 317 | depends on HAVE_ACPI_TABLES |
| 318 | help |
| 319 | Report Machine Check errors identified in POST to the OS in an |
| 320 | ACPI Boot Error Record Table. This option reserves an 8MB region |
| 321 | for building the error structures. |
| 322 | |
Marshall Dawson | 25eb2bc | 2019-03-14 12:42:46 -0600 | [diff] [blame] | 323 | config USE_PSPSECUREOS |
Martin Roth | b617e32 | 2017-09-07 13:23:55 -0600 | [diff] [blame] | 324 | bool "Include PSP SecureOS blobs in AMD firmware" |
| 325 | default y |
| 326 | help |
| 327 | Include the PspSecureOs, PspTrustlet and TrustletKey binaries |
| 328 | in the amdfw section. |
| 329 | |
| 330 | If unsure, answer 'y' |
| 331 | |
Richard Spiegel | 1bc578a | 2019-06-18 18:19:47 -0700 | [diff] [blame] | 332 | config SOC_AMD_PSP_SELECTABLE_SMU_FW |
| 333 | bool |
| 334 | default n if SOC_AMD_MERLINFALCON |
| 335 | default y |
| 336 | help |
| 337 | Some ST implementations allow storing SMU firmware into cbfs and |
| 338 | calling the PSP to load the blobs at the proper time. |
| 339 | |
| 340 | Merlin Falcon does not support it. If you are using 00670F00 SOC, |
| 341 | ask your AMD representative if it supports it or not. |
| 342 | |
Marshall Dawson | 5f0520a | 2017-10-30 16:11:45 -0600 | [diff] [blame] | 343 | config SOC_AMD_SMU_FANLESS |
| 344 | bool |
| 345 | depends on SOC_AMD_PSP_SELECTABLE_SMU_FW |
| 346 | default n if SOC_AMD_SMU_NOTFANLESS |
| 347 | default y |
| 348 | |
| 349 | config SOC_AMD_SMU_FANNED |
| 350 | bool |
| 351 | depends on SOC_AMD_PSP_SELECTABLE_SMU_FW |
| 352 | default n |
| 353 | select SOC_AMD_SMU_NOTFANLESS |
| 354 | |
| 355 | config SOC_AMD_SMU_NOTFANLESS # helper symbol - do not use |
| 356 | bool |
| 357 | depends on SOC_AMD_PSP_SELECTABLE_SMU_FW |
| 358 | |
Martin Roth | 30f9b95 | 2017-10-03 15:54:45 -0600 | [diff] [blame] | 359 | config AMDFW_OUTSIDE_CBFS |
| 360 | bool "The AMD firmware is outside CBFS" |
| 361 | default n |
| 362 | help |
| 363 | The AMDFW (PSP) is typically locatable in cbfs. Select this |
| 364 | option to manually attach the generated amdfw.rom outside of |
| 365 | cbfs. The location is selected by the FWM position. |
| 366 | |
Martin Roth | 6d8ef24 | 2017-09-08 14:39:35 -0600 | [diff] [blame] | 367 | config AMD_FWM_POSITION_INDEX |
| 368 | int "Firmware Directory Table location (0 to 5)" |
| 369 | range 0 5 |
| 370 | default 0 if BOARD_ROMSIZE_KB_512 |
| 371 | default 1 if BOARD_ROMSIZE_KB_1024 |
| 372 | default 2 if BOARD_ROMSIZE_KB_2048 |
| 373 | default 3 if BOARD_ROMSIZE_KB_4096 |
| 374 | default 4 if BOARD_ROMSIZE_KB_8192 |
| 375 | default 5 if BOARD_ROMSIZE_KB_16384 |
| 376 | help |
| 377 | Typically this is calculated by the ROM size, but there may |
| 378 | be situations where you want to put the firmware directory |
| 379 | table in a different location. |
| 380 | 0: 512 KB - 0xFFFA0000 |
| 381 | 1: 1 MB - 0xFFF20000 |
| 382 | 2: 2 MB - 0xFFE20000 |
| 383 | 3: 4 MB - 0xFFC20000 |
| 384 | 4: 8 MB - 0xFF820000 |
| 385 | 5: 16 MB - 0xFF020000 |
| 386 | |
| 387 | comment "AMD Firmware Directory Table set to location for 512KB ROM" |
| 388 | depends on AMD_FWM_POSITION_INDEX = 0 |
| 389 | comment "AMD Firmware Directory Table set to location for 1MB ROM" |
| 390 | depends on AMD_FWM_POSITION_INDEX = 1 |
| 391 | comment "AMD Firmware Directory Table set to location for 2MB ROM" |
| 392 | depends on AMD_FWM_POSITION_INDEX = 2 |
| 393 | comment "AMD Firmware Directory Table set to location for 4MB ROM" |
| 394 | depends on AMD_FWM_POSITION_INDEX = 3 |
| 395 | comment "AMD Firmware Directory Table set to location for 8MB ROM" |
| 396 | depends on AMD_FWM_POSITION_INDEX = 4 |
| 397 | comment "AMD Firmware Directory Table set to location for 16MB ROM" |
| 398 | depends on AMD_FWM_POSITION_INDEX = 5 |
| 399 | |
Marc Jones | 17431ab | 2017-11-16 15:26:00 -0700 | [diff] [blame] | 400 | config DIMM_SPD_SIZE |
| 401 | int |
| 402 | default 512 # DDR4 |
| 403 | |
Marc Jones | 578a79d | 2017-12-06 16:27:04 -0700 | [diff] [blame] | 404 | config RO_REGION_ONLY |
| 405 | string |
| 406 | depends on CHROMEOS |
| 407 | default "apu/amdfw" |
| 408 | |
Chris Ching | 6fc39d4 | 2017-12-20 16:06:03 -0700 | [diff] [blame] | 409 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 410 | int |
| 411 | default 133 |
| 412 | |
Richard Spiegel | 6a38914 | 2018-03-05 14:28:10 -0700 | [diff] [blame] | 413 | config MAINBOARD_POWER_RESTORE |
| 414 | def_bool n |
| 415 | help |
| 416 | This option determines what state to go to once power is restored |
| 417 | after having been lost in S0. Select this option to automatically |
| 418 | return to S0. Otherwise the system will remain in S5 once power |
| 419 | is restored. |
| 420 | |
Richard Spiegel | 1bc578a | 2019-06-18 18:19:47 -0700 | [diff] [blame] | 421 | endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_MERLINFALCON |