Felix Held | 4a8cd72 | 2020-04-18 22:26:39 +0200 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 2 | |
Marshall Dawson | 6851922 | 2019-11-25 11:36:15 -0700 | [diff] [blame] | 3 | config SOC_AMD_STONEYRIDGE |
| 4 | bool |
Kyösti Mälkki | 3139c8d | 2020-06-28 16:33:33 +0300 | [diff] [blame] | 5 | select ACPI_SOC_NVS |
Angel Pons | 8e035e3 | 2021-06-22 12:58:20 +0200 | [diff] [blame] | 6 | select ARCH_X86 |
Felix Held | c07c7c9 | 2020-12-04 18:50:53 +0100 | [diff] [blame] | 7 | select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH |
Aaron Durbin | 51e4c1a | 2018-01-24 17:42:51 -0700 | [diff] [blame] | 8 | select COLLECT_TIMESTAMPS_NO_TSC |
Marc Jones | 9156cac | 2017-07-12 11:05:38 -0600 | [diff] [blame] | 9 | select GENERIC_GPIO_LIB |
Aaron Durbin | 51e4c1a | 2018-01-24 17:42:51 -0700 | [diff] [blame] | 10 | select GENERIC_UDELAY |
Angel Pons | b74975e | 2020-07-13 01:12:57 +0200 | [diff] [blame] | 11 | select HAVE_CF9_RESET |
Felix Held | c07c7c9 | 2020-12-04 18:50:53 +0100 | [diff] [blame] | 12 | select HAVE_SMI_HANDLER |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 13 | select HAVE_USBDEBUG_OPTIONS |
Martin Roth | bcb610a | 2022-10-29 13:31:54 -0600 | [diff] [blame] | 14 | select NO_DDR5 |
| 15 | select NO_DDR3 |
| 16 | select NO_DDR2 |
| 17 | select NO_LPDDR4 |
Marc Jones | 33eef13 | 2017-10-26 16:50:42 -0600 | [diff] [blame] | 18 | select PARALLEL_MP_AP_WORK |
Marc Jones | 17e85ad | 2017-12-20 16:21:25 -0700 | [diff] [blame] | 19 | select RTC |
Felix Held | c07c7c9 | 2020-12-04 18:50:53 +0100 | [diff] [blame] | 20 | select SOC_AMD_PI |
| 21 | select SOC_AMD_COMMON |
| 22 | select SOC_AMD_COMMON_BLOCK_ACPI |
Felix Held | 0bc4684 | 2021-11-23 10:19:28 +0100 | [diff] [blame] | 23 | select SOC_AMD_COMMON_BLOCK_ACPI_GPIO |
Felix Held | c07c7c9 | 2020-12-04 18:50:53 +0100 | [diff] [blame] | 24 | select SOC_AMD_COMMON_BLOCK_ACPIMMIO |
Felix Held | 3136424 | 2021-07-23 19:18:02 +0200 | [diff] [blame] | 25 | select SOC_AMD_COMMON_BLOCK_ACPIMMIO_BIOSRAM |
Felix Held | c07c7c9 | 2020-12-04 18:50:53 +0100 | [diff] [blame] | 26 | select SOC_AMD_COMMON_BLOCK_AOAC |
| 27 | select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS |
| 28 | select SOC_AMD_COMMON_BLOCK_CAR |
Felix Held | 96fd62f | 2023-03-24 16:55:50 +0100 | [diff] [blame] | 29 | select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H |
Felix Held | c07c7c9 | 2020-12-04 18:50:53 +0100 | [diff] [blame] | 30 | select SOC_AMD_COMMON_BLOCK_HDA |
Karthikeyan Ramasubramanian | 0dbea48 | 2021-03-08 23:23:50 -0700 | [diff] [blame] | 31 | select SOC_AMD_COMMON_BLOCK_I2C |
Felix Held | c07c7c9 | 2020-12-04 18:50:53 +0100 | [diff] [blame] | 32 | select SOC_AMD_COMMON_BLOCK_IOMMU |
| 33 | select SOC_AMD_COMMON_BLOCK_LPC |
Felix Held | 1e1d490 | 2021-07-14 00:05:39 +0200 | [diff] [blame] | 34 | select SOC_AMD_COMMON_BLOCK_MCA |
Felix Held | c07c7c9 | 2020-12-04 18:50:53 +0100 | [diff] [blame] | 35 | select SOC_AMD_COMMON_BLOCK_PCI |
Felix Held | c0538d4 | 2021-04-13 19:56:10 +0200 | [diff] [blame] | 36 | select SOC_AMD_COMMON_BLOCK_PM |
Felix Held | c07c7c9 | 2020-12-04 18:50:53 +0100 | [diff] [blame] | 37 | select SOC_AMD_COMMON_BLOCK_PSP_GEN1 |
Felix Held | c07c7c9 | 2020-12-04 18:50:53 +0100 | [diff] [blame] | 38 | select SOC_AMD_COMMON_BLOCK_SATA |
| 39 | select SOC_AMD_COMMON_BLOCK_SMBUS |
| 40 | select SOC_AMD_COMMON_BLOCK_SMI |
Felix Held | bc13481 | 2021-02-10 02:26:10 +0100 | [diff] [blame] | 41 | select SOC_AMD_COMMON_BLOCK_SMM |
Felix Held | 7d8c832 | 2023-03-25 04:59:18 +0100 | [diff] [blame^] | 42 | select SOC_AMD_COMMON_BLOCK_SMN |
Felix Held | c07c7c9 | 2020-12-04 18:50:53 +0100 | [diff] [blame] | 43 | select SOC_AMD_COMMON_BLOCK_SPI |
Felix Held | a3391e5 | 2023-03-24 00:20:02 +0100 | [diff] [blame] | 44 | select SOC_AMD_COMMON_BLOCK_SVI2 |
Felix Held | 91ef925 | 2021-01-12 23:44:05 +0100 | [diff] [blame] | 45 | select SOC_AMD_COMMON_BLOCK_UART |
Felix Held | c07c7c9 | 2020-12-04 18:50:53 +0100 | [diff] [blame] | 46 | select SSE2 |
| 47 | select TSC_SYNC_LFENCE |
Martin Roth | bcb610a | 2022-10-29 13:31:54 -0600 | [diff] [blame] | 48 | select USE_DDR4 |
Felix Held | c07c7c9 | 2020-12-04 18:50:53 +0100 | [diff] [blame] | 49 | select X86_AMD_FIXED_MTRRS |
Elyes Haouas | 3cd06cc | 2023-01-05 07:42:24 +0100 | [diff] [blame] | 50 | help |
| 51 | AMD support for SOCs in Family 15h Models 60h-6Fh and Models 70h-7Fh. |
| 52 | |
| 53 | if SOC_AMD_STONEYRIDGE |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 54 | |
Marshall Dawson | 12294d0 | 2019-11-25 07:21:18 -0700 | [diff] [blame] | 55 | config AMD_APU_STONEYRIDGE |
| 56 | bool |
| 57 | help |
| 58 | AMD Stoney Ridge APU |
| 59 | |
Marshall Dawson | e1988f5 | 2019-11-25 11:15:35 -0700 | [diff] [blame] | 60 | config AMD_APU_PRAIRIEFALCON |
| 61 | bool |
| 62 | help |
| 63 | AMD Embedded Prairie Falcon APU |
| 64 | |
Marshall Dawson | 12294d0 | 2019-11-25 07:21:18 -0700 | [diff] [blame] | 65 | config AMD_APU_MERLINFALCON |
| 66 | bool |
| 67 | help |
Marshall Dawson | e1988f5 | 2019-11-25 11:15:35 -0700 | [diff] [blame] | 68 | AMD Embedded Merlin Falcon APU |
Marshall Dawson | 12294d0 | 2019-11-25 07:21:18 -0700 | [diff] [blame] | 69 | |
Marshall Dawson | 3ac0ab5 | 2019-11-24 19:03:56 -0700 | [diff] [blame] | 70 | config AMD_APU_PKG_FP4 |
| 71 | bool |
| 72 | help |
| 73 | AMD FP4 package |
| 74 | |
| 75 | config AMD_APU_PKG_FT4 |
| 76 | bool |
| 77 | help |
| 78 | AMD FT4 package |
| 79 | |
| 80 | config AMD_SOC_PACKAGE |
| 81 | string |
| 82 | default "FP4" if AMD_APU_PKG_FP4 |
| 83 | default "FT4" if AMD_APU_PKG_FT4 |
| 84 | |
Felix Held | b68e224 | 2022-10-12 18:44:06 +0200 | [diff] [blame] | 85 | config CHIPSET_DEVICETREE |
| 86 | string |
| 87 | default "soc/amd/stoneyridge/chipset_cz.cb" if AMD_APU_MERLINFALCON |
| 88 | default "soc/amd/stoneyridge/chipset_st.cb" if AMD_APU_PRAIRIEFALCON |
| 89 | default "soc/amd/stoneyridge/chipset_st.cb" if AMD_APU_STONEYRIDGE |
| 90 | |
Marshall Dawson | e7557de | 2017-06-09 16:35:14 -0600 | [diff] [blame] | 91 | config VBOOT |
Marshall Dawson | e7557de | 2017-06-09 16:35:14 -0600 | [diff] [blame] | 92 | select VBOOT_STARTS_IN_BOOTBLOCK |
Marc Jones | 4c887ea | 2018-04-25 16:43:18 -0600 | [diff] [blame] | 93 | select VBOOT_VBNV_CMOS |
| 94 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
Marshall Dawson | e7557de | 2017-06-09 16:35:14 -0600 | [diff] [blame] | 95 | |
Marc Jones | 21cde8b | 2017-05-07 16:47:36 -0600 | [diff] [blame] | 96 | # TODO: Sync these with definitions in PI vendorcode. |
| 97 | # DCACHE_RAM_BASE must equal BSP_STACK_BASE_ADDR. |
| 98 | # DCACHE_RAM_SIZE must equal BSP_STACK_SIZE. |
| 99 | |
| 100 | config DCACHE_RAM_BASE |
| 101 | hex |
| 102 | default 0x30000 |
| 103 | |
| 104 | config DCACHE_RAM_SIZE |
| 105 | hex |
| 106 | default 0x10000 |
| 107 | |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 108 | config DCACHE_BSP_STACK_SIZE |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 109 | hex |
| 110 | default 0x4000 |
| 111 | help |
| 112 | The amount of anticipated stack usage in CAR by bootblock and |
| 113 | other stages. |
| 114 | |
Marshall Dawson | 7c3f1e7 | 2017-08-24 09:59:10 -0600 | [diff] [blame] | 115 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 116 | hex |
Marshall Dawson | 1df6bc6 | 2017-12-19 20:41:29 -0700 | [diff] [blame] | 117 | default 0x1600 |
Marshall Dawson | 7c3f1e7 | 2017-08-24 09:59:10 -0600 | [diff] [blame] | 118 | help |
| 119 | Increase this value if preram cbmem console is getting truncated |
| 120 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 121 | config BOTTOMIO_POSITION |
| 122 | hex "Bottom of 32-bit IO space" |
| 123 | default 0xD0000000 |
| 124 | help |
| 125 | If PCI peripherals with big BARs are connected to the system |
| 126 | the bottom of the IO must be decreased to allocate such |
| 127 | devices. |
| 128 | |
| 129 | Declare the beginning of the 128MB-aligned MMIO region. This |
| 130 | option is useful when PCI peripherals requesting large address |
| 131 | ranges are present. |
| 132 | |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 133 | config ECAM_MMCONF_BASE_ADDRESS |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 134 | default 0xF8000000 |
| 135 | |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 136 | config ECAM_MMCONF_BUS_NUMBER |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 137 | default 64 |
| 138 | |
| 139 | config VGA_BIOS_ID |
| 140 | string |
Felix Held | 0b03c08 | 2023-03-24 22:49:48 +0100 | [diff] [blame] | 141 | default "1002,9870" if AMD_APU_MERLINFALCON |
| 142 | default "1002,98e0" |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 143 | help |
| 144 | The default VGA BIOS PCI vendor/device ID should be set to the |
| 145 | result of the map_oprom_vendev() function in northbridge.c. |
| 146 | |
| 147 | config VGA_BIOS_FILE |
| 148 | string |
Marshall Dawson | 7987c1c | 2019-11-25 08:29:28 -0700 | [diff] [blame] | 149 | default "3rdparty/amd_blobs/stoneyridge/CarrizoGenericVbios.bin" if AMD_APU_MERLINFALCON |
Marshall Dawson | e1988f5 | 2019-11-25 11:15:35 -0700 | [diff] [blame] | 150 | default "3rdparty/amd_blobs/stoneyridge/StoneyGenericVbios.bin" if AMD_APU_PRAIRIEFALCON |
| 151 | default "3rdparty/amd_blobs/stoneyridge/StoneyGenericVbios.bin" if AMD_APU_STONEYRIDGE |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 152 | |
Marshall Dawson | 668dea0 | 2017-11-29 09:57:15 -0700 | [diff] [blame] | 153 | config S3_VGA_ROM_RUN |
| 154 | bool |
| 155 | default n |
| 156 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 157 | config HEAP_SIZE |
| 158 | hex |
| 159 | default 0xc0000 |
| 160 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 161 | config EHCI_BAR |
| 162 | hex |
| 163 | default 0xfef00000 |
| 164 | |
| 165 | config STONEYRIDGE_XHCI_ENABLE |
| 166 | bool "Enable Stoney Ridge XHCI Controller" |
| 167 | default y |
| 168 | help |
| 169 | The XHCI controller must be enabled and the XHCI firmware |
| 170 | must be added in order to have USB 3.0 support configured |
| 171 | by coreboot. The OS will be responsible for enabling the XHCI |
Jonathan Neuschäfer | 45e6c82 | 2018-12-11 17:53:07 +0100 | [diff] [blame] | 172 | controller if the XHCI firmware is available but the |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 173 | XHCI controller is not enabled by coreboot. |
| 174 | |
| 175 | config STONEYRIDGE_XHCI_FWM |
| 176 | bool "Add xhci firmware" |
| 177 | default y |
| 178 | help |
| 179 | Add Stoney Ridge XHCI Firmware to support the onboard USB 3.0 |
| 180 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 181 | config STONEYRIDGE_GEC_FWM |
| 182 | bool |
| 183 | default n |
| 184 | help |
| 185 | Add Stoney Ridge GEC Firmware to support the onboard gigabit Ethernet MAC. |
| 186 | Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard. |
| 187 | |
| 188 | config STONEYRIDGE_XHCI_FWM_FILE |
| 189 | string "XHCI firmware path and filename" |
Marshall Dawson | 7987c1c | 2019-11-25 08:29:28 -0700 | [diff] [blame] | 190 | default "3rdparty/amd_blobs/stoneyridge/xhci.bin" |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 191 | depends on STONEYRIDGE_XHCI_FWM |
| 192 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 193 | config STONEYRIDGE_GEC_FWM_FILE |
| 194 | string "GEC firmware path and filename" |
| 195 | depends on STONEYRIDGE_GEC_FWM |
| 196 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 197 | config AMDFW_CONFIG_FILE |
| 198 | string |
| 199 | string "AMD PSP Firmware config file" |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 200 | default "src/soc/amd/stoneyridge/fw_cz.cfg" if AMD_APU_MERLINFALCON |
| 201 | default "src/soc/amd/stoneyridge/fw_st.cfg" if AMD_APU_PRAIRIEFALCON |
| 202 | default "src/soc/amd/stoneyridge/fw_st.cfg" if AMD_APU_STONEYRIDGE |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 203 | |
| 204 | config STONEYRIDGE_SATA_MODE |
| 205 | int "SATA Mode" |
| 206 | default 0 |
| 207 | range 0 6 |
| 208 | help |
| 209 | Select the mode in which SATA should be driven. |
| 210 | The default is NATIVE. |
| 211 | 0: NATIVE mode does not require a ROM. |
| 212 | 2: AHCI may work with or without AHCI ROM. It depends on the payload support. |
| 213 | For example, seabios does not require the AHCI ROM. |
| 214 | 3: LEGACY IDE |
| 215 | 4: IDE to AHCI |
| 216 | 5: AHCI7804: ROM Required, and AMD driver required in the OS. |
| 217 | 6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS. |
| 218 | |
| 219 | comment "NATIVE" |
| 220 | depends on STONEYRIDGE_SATA_MODE = 0 |
| 221 | |
| 222 | comment "AHCI" |
| 223 | depends on STONEYRIDGE_SATA_MODE = 2 |
| 224 | |
| 225 | comment "LEGACY IDE" |
| 226 | depends on STONEYRIDGE_SATA_MODE = 3 |
| 227 | |
| 228 | comment "IDE to AHCI" |
| 229 | depends on STONEYRIDGE_SATA_MODE = 4 |
| 230 | |
| 231 | comment "AHCI7804" |
| 232 | depends on STONEYRIDGE_SATA_MODE = 5 |
| 233 | |
| 234 | comment "IDE to AHCI7804" |
| 235 | depends on STONEYRIDGE_SATA_MODE = 6 |
| 236 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 237 | config STONEYRIDGE_LEGACY_FREE |
| 238 | bool "System is legacy free" |
| 239 | help |
| 240 | Select y if there is no keyboard controller in the system. |
| 241 | This sets variables in AGESA and ACPI. |
| 242 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 243 | config SERIRQ_CONTINUOUS_MODE |
| 244 | bool |
| 245 | default n |
| 246 | help |
| 247 | Set this option to y for serial IRQ in continuous mode. |
| 248 | Otherwise it is in quiet mode. |
| 249 | |
Arthur Heymans | b5e72b6 | 2018-01-02 23:41:24 +0100 | [diff] [blame] | 250 | config CONSOLE_UART_BASE_ADDRESS |
| 251 | depends on CONSOLE_SERIAL |
| 252 | hex |
| 253 | default 0xfedc6000 |
| 254 | |
Marshall Dawson | c6ef9db | 2017-05-14 14:16:56 -0600 | [diff] [blame] | 255 | config SMM_TSEG_SIZE |
| 256 | hex |
Felix Held | e22eef7 | 2021-02-10 22:22:07 +0100 | [diff] [blame] | 257 | default 0x800000 if HAVE_SMI_HANDLER |
Marshall Dawson | c6ef9db | 2017-05-14 14:16:56 -0600 | [diff] [blame] | 258 | default 0x0 |
| 259 | |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 260 | config SMM_RESERVED_SIZE |
| 261 | hex |
Marshall Dawson | fceac7e | 2018-05-18 14:40:53 -0600 | [diff] [blame] | 262 | default 0x150000 |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 263 | |
Raul E Rangel | 846b494 | 2018-06-12 10:43:09 -0600 | [diff] [blame] | 264 | config SMM_MODULE_STACK_SIZE |
| 265 | hex |
| 266 | default 0x800 |
| 267 | |
Marc Jones | e013df9 | 2017-08-23 16:28:02 -0600 | [diff] [blame] | 268 | config ACPI_CPU_STRING |
| 269 | string |
Matt DeVillier | c08d4c5 | 2020-06-20 23:45:30 -0500 | [diff] [blame] | 270 | default "\\_SB.P%03d" |
Marc Jones | e013df9 | 2017-08-23 16:28:02 -0600 | [diff] [blame] | 271 | |
Marshall Dawson | 9a32c41 | 2018-09-04 13:29:12 -0600 | [diff] [blame] | 272 | config ACPI_BERT |
| 273 | bool "Build ACPI BERT Table" |
| 274 | default y |
| 275 | depends on HAVE_ACPI_TABLES |
| 276 | help |
| 277 | Report Machine Check errors identified in POST to the OS in an |
| 278 | ACPI Boot Error Record Table. This option reserves an 8MB region |
| 279 | for building the error structures. |
| 280 | |
Marshall Dawson | 25eb2bc | 2019-03-14 12:42:46 -0600 | [diff] [blame] | 281 | config USE_PSPSECUREOS |
Martin Roth | b617e32 | 2017-09-07 13:23:55 -0600 | [diff] [blame] | 282 | bool "Include PSP SecureOS blobs in AMD firmware" |
| 283 | default y |
| 284 | help |
| 285 | Include the PspSecureOs, PspTrustlet and TrustletKey binaries |
| 286 | in the amdfw section. |
| 287 | |
| 288 | If unsure, answer 'y' |
| 289 | |
Richard Spiegel | 1bc578a | 2019-06-18 18:19:47 -0700 | [diff] [blame] | 290 | config SOC_AMD_PSP_SELECTABLE_SMU_FW |
| 291 | bool |
Marshall Dawson | 12294d0 | 2019-11-25 07:21:18 -0700 | [diff] [blame] | 292 | default y if AMD_APU_STONEYRIDGE |
Richard Spiegel | 1bc578a | 2019-06-18 18:19:47 -0700 | [diff] [blame] | 293 | help |
| 294 | Some ST implementations allow storing SMU firmware into cbfs and |
| 295 | calling the PSP to load the blobs at the proper time. |
| 296 | |
| 297 | Merlin Falcon does not support it. If you are using 00670F00 SOC, |
| 298 | ask your AMD representative if it supports it or not. |
| 299 | |
Marshall Dawson | 5f0520a | 2017-10-30 16:11:45 -0600 | [diff] [blame] | 300 | config SOC_AMD_SMU_FANLESS |
| 301 | bool |
| 302 | depends on SOC_AMD_PSP_SELECTABLE_SMU_FW |
| 303 | default n if SOC_AMD_SMU_NOTFANLESS |
| 304 | default y |
| 305 | |
| 306 | config SOC_AMD_SMU_FANNED |
| 307 | bool |
| 308 | depends on SOC_AMD_PSP_SELECTABLE_SMU_FW |
| 309 | default n |
| 310 | select SOC_AMD_SMU_NOTFANLESS |
| 311 | |
| 312 | config SOC_AMD_SMU_NOTFANLESS # helper symbol - do not use |
| 313 | bool |
| 314 | depends on SOC_AMD_PSP_SELECTABLE_SMU_FW |
| 315 | |
Martin Roth | 30f9b95 | 2017-10-03 15:54:45 -0600 | [diff] [blame] | 316 | config AMDFW_OUTSIDE_CBFS |
| 317 | bool "The AMD firmware is outside CBFS" |
| 318 | default n |
| 319 | help |
| 320 | The AMDFW (PSP) is typically locatable in cbfs. Select this |
| 321 | option to manually attach the generated amdfw.rom outside of |
| 322 | cbfs. The location is selected by the FWM position. |
| 323 | |
Martin Roth | 6d8ef24 | 2017-09-08 14:39:35 -0600 | [diff] [blame] | 324 | config AMD_FWM_POSITION_INDEX |
| 325 | int "Firmware Directory Table location (0 to 5)" |
| 326 | range 0 5 |
| 327 | default 0 if BOARD_ROMSIZE_KB_512 |
| 328 | default 1 if BOARD_ROMSIZE_KB_1024 |
| 329 | default 2 if BOARD_ROMSIZE_KB_2048 |
| 330 | default 3 if BOARD_ROMSIZE_KB_4096 |
| 331 | default 4 if BOARD_ROMSIZE_KB_8192 |
| 332 | default 5 if BOARD_ROMSIZE_KB_16384 |
| 333 | help |
| 334 | Typically this is calculated by the ROM size, but there may |
| 335 | be situations where you want to put the firmware directory |
| 336 | table in a different location. |
| 337 | 0: 512 KB - 0xFFFA0000 |
| 338 | 1: 1 MB - 0xFFF20000 |
| 339 | 2: 2 MB - 0xFFE20000 |
| 340 | 3: 4 MB - 0xFFC20000 |
| 341 | 4: 8 MB - 0xFF820000 |
| 342 | 5: 16 MB - 0xFF020000 |
| 343 | |
| 344 | comment "AMD Firmware Directory Table set to location for 512KB ROM" |
| 345 | depends on AMD_FWM_POSITION_INDEX = 0 |
| 346 | comment "AMD Firmware Directory Table set to location for 1MB ROM" |
| 347 | depends on AMD_FWM_POSITION_INDEX = 1 |
| 348 | comment "AMD Firmware Directory Table set to location for 2MB ROM" |
| 349 | depends on AMD_FWM_POSITION_INDEX = 2 |
| 350 | comment "AMD Firmware Directory Table set to location for 4MB ROM" |
| 351 | depends on AMD_FWM_POSITION_INDEX = 3 |
| 352 | comment "AMD Firmware Directory Table set to location for 8MB ROM" |
| 353 | depends on AMD_FWM_POSITION_INDEX = 4 |
| 354 | comment "AMD Firmware Directory Table set to location for 16MB ROM" |
| 355 | depends on AMD_FWM_POSITION_INDEX = 5 |
| 356 | |
Marc Jones | 17431ab | 2017-11-16 15:26:00 -0700 | [diff] [blame] | 357 | config DIMM_SPD_SIZE |
Marc Jones | 17431ab | 2017-11-16 15:26:00 -0700 | [diff] [blame] | 358 | default 512 # DDR4 |
| 359 | |
Marc Jones | 578a79d | 2017-12-06 16:27:04 -0700 | [diff] [blame] | 360 | config RO_REGION_ONLY |
| 361 | string |
Matt DeVillier | 1e54a18 | 2022-10-04 16:34:21 -0500 | [diff] [blame] | 362 | depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A |
Marc Jones | 578a79d | 2017-12-06 16:27:04 -0700 | [diff] [blame] | 363 | default "apu/amdfw" |
| 364 | |
Chris Ching | 6fc39d4 | 2017-12-20 16:06:03 -0700 | [diff] [blame] | 365 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 366 | int |
| 367 | default 133 |
| 368 | |
Felix Held | 27b295b | 2021-03-25 01:20:41 +0100 | [diff] [blame] | 369 | config DISABLE_KEYBOARD_RESET_PIN |
| 370 | bool |
| 371 | help |
| 372 | Instruct the SoC to not use the state of GPIO_129 as keyboard reset |
| 373 | signal. When this pin is used as GPIO and the keyboard reset |
| 374 | functionality isn't disabled, configuring it as an output and driving |
| 375 | it as 0 will cause a reset. |
| 376 | |
Arthur Heymans | dd7ec09 | 2022-05-23 16:06:06 +0200 | [diff] [blame] | 377 | config ACPI_BERT_SIZE |
| 378 | hex |
| 379 | default 0x100000 if ACPI_BERT |
| 380 | default 0x0 |
| 381 | help |
| 382 | Specify the amount of DRAM reserved for gathering the data used to |
| 383 | generate the ACPI table. |
| 384 | |
Marshall Dawson | 6851922 | 2019-11-25 11:36:15 -0700 | [diff] [blame] | 385 | endif # SOC_AMD_STONEYRIDGE |