Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2017 Advanced Micro Devices, Inc. |
| 5 | ## |
| 6 | ## This program is free software; you can redistribute it and/or modify |
| 7 | ## it under the terms of the GNU General Public License as published by |
| 8 | ## the Free Software Foundation; version 2 of the License. |
| 9 | ## |
| 10 | ## This program is distributed in the hope that it will be useful, |
| 11 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | ## GNU General Public License for more details. |
| 14 | ## |
| 15 | |
Marc Jones | 21cde8b | 2017-05-07 16:47:36 -0600 | [diff] [blame] | 16 | config SOC_AMD_STONEYRIDGE_FP4 |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 17 | bool |
Marc Jones | 21cde8b | 2017-05-07 16:47:36 -0600 | [diff] [blame] | 18 | help |
| 19 | AMD Stoney Ridge FP4 support |
| 20 | |
| 21 | config SOC_AMD_STONEYRIDGE_FT4 |
| 22 | bool |
| 23 | help |
| 24 | AMD Stoney Ridge FT4 support |
| 25 | |
| 26 | if SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 |
| 27 | |
| 28 | config CPU_SPECIFIC_OPTIONS |
| 29 | def_bool y |
| 30 | select ARCH_BOOTBLOCK_X86_32 |
| 31 | select ARCH_VERSTAGE_X86_32 |
| 32 | select ARCH_ROMSTAGE_X86_32 |
| 33 | select ARCH_RAMSTAGE_X86_32 |
Marshall Dawson | 82145a1 | 2017-10-20 12:36:35 -0600 | [diff] [blame] | 34 | select X86_AMD_FIXED_MTRRS |
Marshall Dawson | 68592c3 | 2017-11-06 10:56:52 -0700 | [diff] [blame] | 35 | select ACPI_AMD_HARDWARE_SLEEP_VALUES |
Aaron Durbin | 51e4c1a | 2018-01-24 17:42:51 -0700 | [diff] [blame] | 36 | select COLLECT_TIMESTAMPS_NO_TSC |
Chris Ching | 6fc39d4 | 2017-12-20 16:06:03 -0700 | [diff] [blame] | 37 | select DRIVERS_I2C_DESIGNWARE |
Marc Jones | 9156cac | 2017-07-12 11:05:38 -0600 | [diff] [blame] | 38 | select GENERIC_GPIO_LIB |
Aaron Durbin | 51e4c1a | 2018-01-24 17:42:51 -0700 | [diff] [blame] | 39 | select GENERIC_UDELAY |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 40 | select IOAPIC |
| 41 | select HAVE_USBDEBUG_OPTIONS |
| 42 | select HAVE_HARD_RESET |
Marshall Dawson | 786bd5d | 2017-06-16 10:10:17 -0600 | [diff] [blame] | 43 | select HAVE_MONOTONIC_TIMER |
Marc Jones | 21cde8b | 2017-05-07 16:47:36 -0600 | [diff] [blame] | 44 | select SPI_FLASH if HAVE_ACPI_RESUME |
| 45 | select TSC_SYNC_LFENCE |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 46 | select COLLECT_TIMESTAMPS |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 47 | select SOC_AMD_PI |
Marshall Dawson | 68243a5 | 2017-06-15 16:59:20 -0600 | [diff] [blame] | 48 | select SOC_AMD_COMMON |
| 49 | select SOC_AMD_COMMON_BLOCK |
Richard Spiegel | 2bbc3dc | 2017-12-06 16:14:58 -0700 | [diff] [blame] | 50 | select SOC_AMD_COMMON_BLOCK_PCI |
Richard Spiegel | 19f67a3 | 2017-12-08 18:16:02 -0700 | [diff] [blame] | 51 | select SOC_AMD_COMMON_BLOCK_PI |
Marshall Dawson | 68243a5 | 2017-06-15 16:59:20 -0600 | [diff] [blame] | 52 | select SOC_AMD_COMMON_BLOCK_PSP |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 53 | select SOC_AMD_COMMON_BLOCK_CAR |
Marshall Dawson | 8f2a7e0 | 2017-11-01 11:44:48 -0600 | [diff] [blame] | 54 | select SOC_AMD_COMMON_BLOCK_S3 if HAVE_ACPI_RESUME |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 55 | select C_ENVIRONMENT_BOOTBLOCK |
| 56 | select BOOTBLOCK_CONSOLE |
John E. Kabat Jr | af32770 | 2017-11-29 18:49:37 -0700 | [diff] [blame] | 57 | select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH |
Marc Jones | 4c887ea | 2018-04-25 16:43:18 -0600 | [diff] [blame] | 58 | select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH |
Marshall Dawson | f3c57a7c | 2018-01-29 18:08:16 -0700 | [diff] [blame] | 59 | select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 60 | select PARALLEL_MP |
Marc Jones | 33eef13 | 2017-10-26 16:50:42 -0600 | [diff] [blame] | 61 | select PARALLEL_MP_AP_WORK |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 62 | select HAVE_SMI_HANDLER |
| 63 | select SMM_TSEG |
Marshall Dawson | 18b477e | 2017-09-21 12:27:12 -0600 | [diff] [blame] | 64 | select POSTCAR_STAGE |
| 65 | select POSTCAR_CONSOLE |
Martin Roth | 37b8bde | 2017-09-26 09:41:10 -0600 | [diff] [blame] | 66 | select SSE |
| 67 | select SSE2 |
Marc Jones | 17e85ad | 2017-12-20 16:21:25 -0700 | [diff] [blame] | 68 | select RTC |
Richard Spiegel | 3870dd9 | 2018-08-03 10:36:13 -0700 | [diff] [blame] | 69 | select SOC_AMD_PSP_SELECTABLE_SMU_FW |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 70 | |
Marshall Dawson | e7557de | 2017-06-09 16:35:14 -0600 | [diff] [blame] | 71 | config VBOOT |
Marshall Dawson | e7557de | 2017-06-09 16:35:14 -0600 | [diff] [blame] | 72 | select VBOOT_SEPARATE_VERSTAGE |
| 73 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 74 | select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT |
Marc Jones | 4c887ea | 2018-04-25 16:43:18 -0600 | [diff] [blame] | 75 | select VBOOT_VBNV_CMOS |
| 76 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
Marshall Dawson | e7557de | 2017-06-09 16:35:14 -0600 | [diff] [blame] | 77 | |
Marc Jones | 21cde8b | 2017-05-07 16:47:36 -0600 | [diff] [blame] | 78 | config UDELAY_LAPIC_FIXED_FSB |
| 79 | int |
| 80 | default 200 |
| 81 | |
| 82 | # TODO: Sync these with definitions in PI vendorcode. |
| 83 | # DCACHE_RAM_BASE must equal BSP_STACK_BASE_ADDR. |
| 84 | # DCACHE_RAM_SIZE must equal BSP_STACK_SIZE. |
| 85 | |
| 86 | config DCACHE_RAM_BASE |
| 87 | hex |
| 88 | default 0x30000 |
| 89 | |
| 90 | config DCACHE_RAM_SIZE |
| 91 | hex |
| 92 | default 0x10000 |
| 93 | |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 94 | config DCACHE_BSP_STACK_SIZE |
| 95 | depends on C_ENVIRONMENT_BOOTBLOCK |
| 96 | hex |
| 97 | default 0x4000 |
| 98 | help |
| 99 | The amount of anticipated stack usage in CAR by bootblock and |
| 100 | other stages. |
| 101 | |
Marshall Dawson | 7c3f1e7 | 2017-08-24 09:59:10 -0600 | [diff] [blame] | 102 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 103 | hex |
Marshall Dawson | 1df6bc6 | 2017-12-19 20:41:29 -0700 | [diff] [blame] | 104 | default 0x1600 |
Marshall Dawson | 7c3f1e7 | 2017-08-24 09:59:10 -0600 | [diff] [blame] | 105 | help |
| 106 | Increase this value if preram cbmem console is getting truncated |
| 107 | |
Marc Jones | 21cde8b | 2017-05-07 16:47:36 -0600 | [diff] [blame] | 108 | config CPU_ADDR_BITS |
| 109 | int |
| 110 | default 48 |
| 111 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 112 | config BOTTOMIO_POSITION |
| 113 | hex "Bottom of 32-bit IO space" |
| 114 | default 0xD0000000 |
| 115 | help |
| 116 | If PCI peripherals with big BARs are connected to the system |
| 117 | the bottom of the IO must be decreased to allocate such |
| 118 | devices. |
| 119 | |
| 120 | Declare the beginning of the 128MB-aligned MMIO region. This |
| 121 | option is useful when PCI peripherals requesting large address |
| 122 | ranges are present. |
| 123 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 124 | config MMCONF_BASE_ADDRESS |
| 125 | hex |
| 126 | default 0xF8000000 |
| 127 | |
| 128 | config MMCONF_BUS_NUMBER |
| 129 | int |
| 130 | default 64 |
| 131 | |
| 132 | config VGA_BIOS_ID |
| 133 | string |
| 134 | default "1002,98e4" |
| 135 | help |
| 136 | The default VGA BIOS PCI vendor/device ID should be set to the |
| 137 | result of the map_oprom_vendev() function in northbridge.c. |
| 138 | |
| 139 | config VGA_BIOS_FILE |
| 140 | string |
Richard Spiegel | 4eaf0fa | 2018-01-23 15:51:57 -0700 | [diff] [blame] | 141 | default "3rdparty/blobs/soc/amd/stoneyridge/VBIOS.bin" |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 142 | |
Marshall Dawson | 668dea0 | 2017-11-29 09:57:15 -0700 | [diff] [blame] | 143 | config S3_VGA_ROM_RUN |
| 144 | bool |
| 145 | default n |
| 146 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 147 | config HEAP_SIZE |
| 148 | hex |
| 149 | default 0xc0000 |
| 150 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 151 | config SOUTHBRIDGE_AMD_STONEYRIDGE_SKIP_ISA_DMA_INIT |
| 152 | bool |
| 153 | default n |
| 154 | |
| 155 | config EHCI_BAR |
| 156 | hex |
| 157 | default 0xfef00000 |
| 158 | |
| 159 | config STONEYRIDGE_XHCI_ENABLE |
| 160 | bool "Enable Stoney Ridge XHCI Controller" |
| 161 | default y |
| 162 | help |
| 163 | The XHCI controller must be enabled and the XHCI firmware |
| 164 | must be added in order to have USB 3.0 support configured |
| 165 | by coreboot. The OS will be responsible for enabling the XHCI |
| 166 | controller if the the XHCI firmware is available but the |
| 167 | XHCI controller is not enabled by coreboot. |
| 168 | |
| 169 | config STONEYRIDGE_XHCI_FWM |
| 170 | bool "Add xhci firmware" |
| 171 | default y |
| 172 | help |
| 173 | Add Stoney Ridge XHCI Firmware to support the onboard USB 3.0 |
| 174 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 175 | config STONEYRIDGE_GEC_FWM |
| 176 | bool |
| 177 | default n |
| 178 | help |
| 179 | Add Stoney Ridge GEC Firmware to support the onboard gigabit Ethernet MAC. |
| 180 | Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard. |
| 181 | |
| 182 | config STONEYRIDGE_XHCI_FWM_FILE |
| 183 | string "XHCI firmware path and filename" |
Richard Spiegel | a987278 | 2018-01-04 17:26:54 -0700 | [diff] [blame] | 184 | default "3rdparty/blobs/soc/amd/stoneyridge/xhci.bin" |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 185 | depends on STONEYRIDGE_XHCI_FWM |
| 186 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 187 | config STONEYRIDGE_GEC_FWM_FILE |
| 188 | string "GEC firmware path and filename" |
| 189 | depends on STONEYRIDGE_GEC_FWM |
| 190 | |
| 191 | config AMD_PUBKEY_FILE |
| 192 | string "AMD public Key" |
Richard Spiegel | a987278 | 2018-01-04 17:26:54 -0700 | [diff] [blame] | 193 | default "3rdparty/blobs/soc/amd/stoneyridge/PSP/AmdPubKeyST.bin" |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 194 | |
| 195 | config STONEYRIDGE_SATA_MODE |
| 196 | int "SATA Mode" |
| 197 | default 0 |
| 198 | range 0 6 |
| 199 | help |
| 200 | Select the mode in which SATA should be driven. |
| 201 | The default is NATIVE. |
| 202 | 0: NATIVE mode does not require a ROM. |
| 203 | 2: AHCI may work with or without AHCI ROM. It depends on the payload support. |
| 204 | For example, seabios does not require the AHCI ROM. |
| 205 | 3: LEGACY IDE |
| 206 | 4: IDE to AHCI |
| 207 | 5: AHCI7804: ROM Required, and AMD driver required in the OS. |
| 208 | 6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS. |
| 209 | |
| 210 | comment "NATIVE" |
| 211 | depends on STONEYRIDGE_SATA_MODE = 0 |
| 212 | |
| 213 | comment "AHCI" |
| 214 | depends on STONEYRIDGE_SATA_MODE = 2 |
| 215 | |
| 216 | comment "LEGACY IDE" |
| 217 | depends on STONEYRIDGE_SATA_MODE = 3 |
| 218 | |
| 219 | comment "IDE to AHCI" |
| 220 | depends on STONEYRIDGE_SATA_MODE = 4 |
| 221 | |
| 222 | comment "AHCI7804" |
| 223 | depends on STONEYRIDGE_SATA_MODE = 5 |
| 224 | |
| 225 | comment "IDE to AHCI7804" |
| 226 | depends on STONEYRIDGE_SATA_MODE = 6 |
| 227 | |
| 228 | if STONEYRIDGE_SATA_MODE = 2 || STONEYRIDGE_SATA_MODE = 5 |
| 229 | |
| 230 | config AHCI_ROM_ID |
| 231 | string "AHCI device PCI IDs" |
| 232 | default "1022,7801" if STONEYRIDGE_SATA_MODE = 2 |
| 233 | default "1022,7804" if STONEYRIDGE_SATA_MODE = 5 |
| 234 | |
| 235 | endif # STONEYRIDGE_SATA_MODE = 2 || STONEYRIDGE_SATA_MODE = 5 |
| 236 | |
| 237 | config STONEYRIDGE_LEGACY_FREE |
| 238 | bool "System is legacy free" |
| 239 | help |
| 240 | Select y if there is no keyboard controller in the system. |
| 241 | This sets variables in AGESA and ACPI. |
| 242 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 243 | config SERIRQ_CONTINUOUS_MODE |
| 244 | bool |
| 245 | default n |
| 246 | help |
| 247 | Set this option to y for serial IRQ in continuous mode. |
| 248 | Otherwise it is in quiet mode. |
| 249 | |
| 250 | config STONEYRIDGE_ACPI_IO_BASE |
| 251 | hex |
| 252 | default 0x400 |
| 253 | help |
| 254 | Base address for the ACPI registers. |
| 255 | This value must match the hardcoded value of AGESA. |
| 256 | |
| 257 | config STONEYRIDGE_UART |
| 258 | bool "UART controller on Stoney Ridge" |
| 259 | default n |
| 260 | select DRIVERS_UART_8250MEM |
| 261 | select DRIVERS_UART_8250MEM_32 |
| 262 | select NO_UART_ON_SUPERIO |
| 263 | select UART_OVERRIDE_REFCLK |
| 264 | help |
| 265 | There are two UART controllers in Stoney Ridge. |
| 266 | The UART registers are memory-mapped. UART |
| 267 | controller 0 registers range from FEDC_6000h |
| 268 | to FEDC_6FFFh. UART controller 1 registers |
| 269 | range from FEDC_8000h to FEDC_8FFFh. |
| 270 | |
Arthur Heymans | b5e72b6 | 2018-01-02 23:41:24 +0100 | [diff] [blame] | 271 | config CONSOLE_UART_BASE_ADDRESS |
| 272 | depends on CONSOLE_SERIAL |
| 273 | hex |
| 274 | default 0xfedc6000 |
| 275 | |
Marshall Dawson | c6ef9db | 2017-05-14 14:16:56 -0600 | [diff] [blame] | 276 | config SMM_TSEG_SIZE |
| 277 | hex |
Marshall Dawson | 0801b33 | 2017-08-25 15:29:45 -0600 | [diff] [blame] | 278 | default 0x800000 if SMM_TSEG && HAVE_SMI_HANDLER |
Marshall Dawson | c6ef9db | 2017-05-14 14:16:56 -0600 | [diff] [blame] | 279 | default 0x0 |
| 280 | |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 281 | config SMM_RESERVED_SIZE |
| 282 | hex |
Marshall Dawson | fceac7e | 2018-05-18 14:40:53 -0600 | [diff] [blame] | 283 | default 0x150000 |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 284 | |
Raul E Rangel | 846b494 | 2018-06-12 10:43:09 -0600 | [diff] [blame] | 285 | config SMM_MODULE_STACK_SIZE |
| 286 | hex |
| 287 | default 0x800 |
| 288 | |
Marc Jones | e013df9 | 2017-08-23 16:28:02 -0600 | [diff] [blame] | 289 | config ACPI_CPU_STRING |
| 290 | string |
| 291 | default "\\_PR.P%03d" |
| 292 | |
Marshall Dawson | 9a32c41 | 2018-09-04 13:29:12 -0600 | [diff] [blame^] | 293 | config ACPI_BERT |
| 294 | bool "Build ACPI BERT Table" |
| 295 | default y |
| 296 | depends on HAVE_ACPI_TABLES |
| 297 | help |
| 298 | Report Machine Check errors identified in POST to the OS in an |
| 299 | ACPI Boot Error Record Table. This option reserves an 8MB region |
| 300 | for building the error structures. |
| 301 | |
Martin Roth | b617e32 | 2017-09-07 13:23:55 -0600 | [diff] [blame] | 302 | config USE_PSPSCUREOS |
| 303 | bool "Include PSP SecureOS blobs in AMD firmware" |
| 304 | default y |
| 305 | help |
| 306 | Include the PspSecureOs, PspTrustlet and TrustletKey binaries |
| 307 | in the amdfw section. |
| 308 | |
| 309 | If unsure, answer 'y' |
| 310 | |
Marshall Dawson | 5f0520a | 2017-10-30 16:11:45 -0600 | [diff] [blame] | 311 | config SOC_AMD_SMU_FANLESS |
| 312 | bool |
| 313 | depends on SOC_AMD_PSP_SELECTABLE_SMU_FW |
| 314 | default n if SOC_AMD_SMU_NOTFANLESS |
| 315 | default y |
| 316 | |
| 317 | config SOC_AMD_SMU_FANNED |
| 318 | bool |
| 319 | depends on SOC_AMD_PSP_SELECTABLE_SMU_FW |
| 320 | default n |
| 321 | select SOC_AMD_SMU_NOTFANLESS |
| 322 | |
| 323 | config SOC_AMD_SMU_NOTFANLESS # helper symbol - do not use |
| 324 | bool |
| 325 | depends on SOC_AMD_PSP_SELECTABLE_SMU_FW |
| 326 | |
Martin Roth | 30f9b95 | 2017-10-03 15:54:45 -0600 | [diff] [blame] | 327 | config AMDFW_OUTSIDE_CBFS |
| 328 | bool "The AMD firmware is outside CBFS" |
| 329 | default n |
| 330 | help |
| 331 | The AMDFW (PSP) is typically locatable in cbfs. Select this |
| 332 | option to manually attach the generated amdfw.rom outside of |
| 333 | cbfs. The location is selected by the FWM position. |
| 334 | |
Martin Roth | 6d8ef24 | 2017-09-08 14:39:35 -0600 | [diff] [blame] | 335 | config AMD_FWM_POSITION_INDEX |
| 336 | int "Firmware Directory Table location (0 to 5)" |
| 337 | range 0 5 |
| 338 | default 0 if BOARD_ROMSIZE_KB_512 |
| 339 | default 1 if BOARD_ROMSIZE_KB_1024 |
| 340 | default 2 if BOARD_ROMSIZE_KB_2048 |
| 341 | default 3 if BOARD_ROMSIZE_KB_4096 |
| 342 | default 4 if BOARD_ROMSIZE_KB_8192 |
| 343 | default 5 if BOARD_ROMSIZE_KB_16384 |
| 344 | help |
| 345 | Typically this is calculated by the ROM size, but there may |
| 346 | be situations where you want to put the firmware directory |
| 347 | table in a different location. |
| 348 | 0: 512 KB - 0xFFFA0000 |
| 349 | 1: 1 MB - 0xFFF20000 |
| 350 | 2: 2 MB - 0xFFE20000 |
| 351 | 3: 4 MB - 0xFFC20000 |
| 352 | 4: 8 MB - 0xFF820000 |
| 353 | 5: 16 MB - 0xFF020000 |
| 354 | |
| 355 | comment "AMD Firmware Directory Table set to location for 512KB ROM" |
| 356 | depends on AMD_FWM_POSITION_INDEX = 0 |
| 357 | comment "AMD Firmware Directory Table set to location for 1MB ROM" |
| 358 | depends on AMD_FWM_POSITION_INDEX = 1 |
| 359 | comment "AMD Firmware Directory Table set to location for 2MB ROM" |
| 360 | depends on AMD_FWM_POSITION_INDEX = 2 |
| 361 | comment "AMD Firmware Directory Table set to location for 4MB ROM" |
| 362 | depends on AMD_FWM_POSITION_INDEX = 3 |
| 363 | comment "AMD Firmware Directory Table set to location for 8MB ROM" |
| 364 | depends on AMD_FWM_POSITION_INDEX = 4 |
| 365 | comment "AMD Firmware Directory Table set to location for 16MB ROM" |
| 366 | depends on AMD_FWM_POSITION_INDEX = 5 |
| 367 | |
Marc Jones | 17431ab | 2017-11-16 15:26:00 -0700 | [diff] [blame] | 368 | config DIMM_SPD_SIZE |
| 369 | int |
| 370 | default 512 # DDR4 |
| 371 | |
Marc Jones | 578a79d | 2017-12-06 16:27:04 -0700 | [diff] [blame] | 372 | config RO_REGION_ONLY |
| 373 | string |
| 374 | depends on CHROMEOS |
| 375 | default "apu/amdfw" |
| 376 | |
Chris Ching | 6fc39d4 | 2017-12-20 16:06:03 -0700 | [diff] [blame] | 377 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 378 | int |
| 379 | default 133 |
| 380 | |
Richard Spiegel | 6a38914 | 2018-03-05 14:28:10 -0700 | [diff] [blame] | 381 | config MAINBOARD_POWER_RESTORE |
| 382 | def_bool n |
| 383 | help |
| 384 | This option determines what state to go to once power is restored |
| 385 | after having been lost in S0. Select this option to automatically |
| 386 | return to S0. Otherwise the system will remain in S5 once power |
| 387 | is restored. |
| 388 | |
Marc Jones | 21cde8b | 2017-05-07 16:47:36 -0600 | [diff] [blame] | 389 | endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 |