Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2011 Google Inc. |
| 5 | ## |
| 6 | ## This program is free software; you can redistribute it and/or modify |
| 7 | ## it under the terms of the GNU General Public License as published by |
| 8 | ## the Free Software Foundation; version 2 of the License. |
| 9 | ## |
| 10 | ## This program is distributed in the hope that it will be useful, |
| 11 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | ## GNU General Public License for more details. |
| 14 | ## |
| 15 | ## You should have received a copy of the GNU General Public License |
| 16 | ## along with this program; if not, write to the Free Software |
Paul Menzel | a46a712 | 2013-02-23 18:37:27 +0100 | [diff] [blame] | 17 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 18 | ## |
| 19 | |
| 20 | config SOUTHBRIDGE_INTEL_BD82X6X |
| 21 | bool |
| 22 | |
| 23 | config SOUTHBRIDGE_INTEL_C216 |
| 24 | bool |
| 25 | |
| 26 | if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216 |
| 27 | |
| 28 | config SOUTH_BRIDGE_OPTIONS # dummy |
| 29 | def_bool y |
| 30 | select IOAPIC |
| 31 | select HAVE_HARD_RESET |
| 32 | select HAVE_USBDEBUG |
Stefan Reinauer | 431a816 | 2012-11-13 13:01:31 -0800 | [diff] [blame] | 33 | select HAVE_SMI_HANDLER |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 34 | select USE_WATCHDOG_ON_BOOT |
| 35 | select PCIEXP_ASPM |
| 36 | select PCIEXP_COMMON_CLOCK |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 37 | select SPI_FLASH |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 38 | |
| 39 | config EHCI_BAR |
| 40 | hex |
| 41 | default 0xfef00000 |
| 42 | |
| 43 | config EHCI_DEBUG_OFFSET |
| 44 | hex |
| 45 | default 0xa0 |
| 46 | |
| 47 | config BOOTBLOCK_SOUTHBRIDGE_INIT |
| 48 | string |
| 49 | default "southbridge/intel/bd82x6x/bootblock.c" |
| 50 | |
| 51 | config SERIRQ_CONTINUOUS_MODE |
| 52 | bool |
| 53 | default n |
| 54 | help |
| 55 | If you set this option to y, the serial IRQ machine will be |
| 56 | operated in continuous mode. |
| 57 | |
Patrick Georgi | 9aeb694 | 2012-10-05 21:54:38 +0200 | [diff] [blame] | 58 | config HPET_MIN_TICKS |
| 59 | hex |
| 60 | default 0x80 |
| 61 | |
Nico Huber | a15cd66 | 2013-06-19 16:16:05 +0200 | [diff] [blame^] | 62 | config HAVE_IFD_BIN |
| 63 | bool |
| 64 | default y |
| 65 | |
| 66 | config BUILD_WITH_FAKE_IFD |
| 67 | bool "Build with a fake IFD" |
| 68 | default y if !HAVE_IFD_BIN |
| 69 | help |
| 70 | If you don't have an Intel Firmware Descriptor (ifd.bin) for your |
| 71 | board, you can select this option and coreboot will build without it. |
| 72 | Though, the resulting coreboot.rom will not contain all parts required |
| 73 | to get coreboot running on your board. You can however write only the |
| 74 | BIOS section to your board's flash ROM and keep the other sections |
| 75 | untouched. Unfortunately the current version of flashrom doesn't |
| 76 | support this yet. But there is a patch pending [1]. |
| 77 | |
| 78 | WARNING: Never write a complete coreboot.rom to your flash ROM if it |
| 79 | was built with a fake IFD. It just won't work. |
| 80 | |
| 81 | [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html |
| 82 | |
| 83 | config IFD_BIOS_SECTION |
| 84 | depends on BUILD_WITH_FAKE_IFD |
| 85 | string |
| 86 | default "" |
| 87 | |
| 88 | config IFD_ME_SECTION |
| 89 | depends on BUILD_WITH_FAKE_IFD |
| 90 | string |
| 91 | default "" |
| 92 | |
| 93 | config IFD_GBE_SECTION |
| 94 | depends on BUILD_WITH_FAKE_IFD |
| 95 | string |
| 96 | default "" |
| 97 | |
| 98 | config IFD_PLATFORM_SECTION |
| 99 | depends on BUILD_WITH_FAKE_IFD |
| 100 | string |
| 101 | default "" |
| 102 | |
| 103 | config IFD_BIN_PATH |
| 104 | string "Path to intel firmware descriptor" |
| 105 | depends on !BUILD_WITH_FAKE_IFD |
| 106 | default "3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin" |
| 107 | |
Nico Huber | ea6d6e8c | 2013-05-14 15:14:08 +0200 | [diff] [blame] | 108 | config HAVE_GBE_BIN |
| 109 | bool "Add gigabit ethernet firmware" |
| 110 | default n |
| 111 | help |
| 112 | The integrated gigabit ethernet controller needs a firmware file. |
| 113 | Select this if you are going to use the PCH integrated controller |
| 114 | and have the firmware. |
| 115 | |
| 116 | config GBE_BIN_PATH |
| 117 | string "Path to gigabit ethernet firmware" |
| 118 | depends on HAVE_GBE_BIN |
| 119 | default "3rdparty/mainboard/$(MAINBOARDDIR)/gbe.bin" |
| 120 | |
Patrick Georgi | 3cc151e | 2013-06-13 15:07:02 +0200 | [diff] [blame] | 121 | config ME_BIN_PATH |
| 122 | string "Path to management engine firmware" |
| 123 | default "3rdparty/mainboard/$(MAINBOARDDIR)/me.bin" |
| 124 | |
Stefan Reinauer | 7004b7c | 2012-10-31 17:30:13 -0700 | [diff] [blame] | 125 | config LOCK_MANAGEMENT_ENGINE |
| 126 | bool "Lock Management Engine section" |
Nico Huber | a15cd66 | 2013-06-19 16:16:05 +0200 | [diff] [blame^] | 127 | depends on !BUILD_WITH_FAKE_IFD |
Stefan Reinauer | 7004b7c | 2012-10-31 17:30:13 -0700 | [diff] [blame] | 128 | default n |
| 129 | help |
| 130 | The Intel Management Engine supports preventing write accesses |
| 131 | from the host to the Management Engine section in the firmware |
| 132 | descriptor. If the ME section is locked, it can only be overwritten |
| 133 | with an external SPI flash programmer. You will want this if you |
| 134 | want to increase security of your ROM image once you are sure |
| 135 | that the ME firmware is no longer going to change. |
| 136 | |
| 137 | If unsure, say N. |
| 138 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 139 | endif |