soc/intel/common: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I09cc69a20dc67c0f48b35bfd2afeaba9e2ee5064
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c
index 7d75bdd..9498060 100644
--- a/src/soc/intel/common/block/uart/uart.c
+++ b/src/soc/intel/common/block/uart/uart.c
@@ -68,7 +68,7 @@
pci_write_config32(dev, PCI_BASE_ADDRESS_0, baseaddr);
/* Enable memory access and bus master */
- pci_write_config32(dev, PCI_COMMAND, UART_PCI_ENABLE);
+ pci_write_config16(dev, PCI_COMMAND, UART_PCI_ENABLE);
uart_lpss_init(device, baseaddr);
}
@@ -109,7 +109,7 @@
if (!base)
return false;
- if ((pci_read_config32(dev, PCI_COMMAND) & UART_PCI_ENABLE)
+ if ((pci_read_config16(dev, PCI_COMMAND) & UART_PCI_ENABLE)
!= UART_PCI_ENABLE)
return false;