Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 1 | config SOC_INTEL_SKYLAKE |
2 | bool | ||||
3 | help | ||||
4 | Intel Skylake support | ||||
5 | |||||
Rizwan Qureshi | 0700dca | 2017-02-09 15:57:45 +0530 | [diff] [blame] | 6 | config SOC_INTEL_KABYLAKE |
7 | bool | ||||
8 | default n | ||||
9 | select SOC_INTEL_SKYLAKE | ||||
10 | help | ||||
11 | Intel Kabylake support | ||||
12 | |||||
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 13 | if SOC_INTEL_SKYLAKE |
14 | |||||
15 | config CPU_SPECIFIC_OPTIONS | ||||
16 | def_bool y | ||||
Aaron Durbin | e0a4914 | 2016-07-13 23:20:51 -0500 | [diff] [blame] | 17 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Vadim Bendebury | 5542bb6 | 2018-02-05 19:59:09 -0800 | [diff] [blame] | 18 | select ACPI_NHLT |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 19 | select ARCH_BOOTBLOCK_X86_32 |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 20 | select ARCH_RAMSTAGE_X86_32 |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 21 | select ARCH_ROMSTAGE_X86_32 |
22 | select ARCH_VERSTAGE_X86_32 | ||||
Teo Boon Tiong | 673a4d0 | 2016-11-10 21:06:51 +0800 | [diff] [blame] | 23 | select BOOTBLOCK_CONSOLE |
Aaron Durbin | e4cc8cd | 2016-08-11 23:55:39 -0500 | [diff] [blame] | 24 | select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH |
Aaron Durbin | e8e118d | 2016-08-12 15:00:10 -0500 | [diff] [blame] | 25 | select BOOT_DEVICE_SUPPORTS_WRITES |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 26 | select CACHE_MRC_SETTINGS |
Kyösti Mälkki | 730df3c | 2016-06-18 07:39:31 +0300 | [diff] [blame] | 27 | select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 28 | select COLLECT_TIMESTAMPS |
Duncan Laurie | 135c2c4 | 2016-10-17 19:47:51 -0700 | [diff] [blame] | 29 | select COMMON_FADT |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 30 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Vadim Bendebury | 5542bb6 | 2018-02-05 19:59:09 -0800 | [diff] [blame] | 31 | select C_ENVIRONMENT_BOOTBLOCK |
Aaron Durbin | ffdf901 | 2015-07-24 13:00:36 -0500 | [diff] [blame] | 32 | select GENERIC_GPIO_LIB |
Vadim Bendebury | 5542bb6 | 2018-02-05 19:59:09 -0800 | [diff] [blame] | 33 | select HAVE_FSP_GOP |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 34 | select HAVE_HARD_RESET |
Stefan Tauner | ef8b957 | 2018-09-06 00:34:28 +0200 | [diff] [blame] | 35 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 36 | select HAVE_MONOTONIC_TIMER |
37 | select HAVE_SMI_HANDLER | ||||
Patrick Rudolph | c7edf18 | 2017-09-26 19:34:35 +0200 | [diff] [blame] | 38 | select INTEL_GMA_ACPI |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 39 | select IOAPIC |
Duncan Laurie | 205ed2d | 2016-06-02 15:23:42 -0700 | [diff] [blame] | 40 | select MRC_SETTINGS_PROTECT |
Vadim Bendebury | 5542bb6 | 2018-02-05 19:59:09 -0800 | [diff] [blame] | 41 | select NO_FIXED_XIP_ROM_SIZE |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 42 | select PARALLEL_MP |
Furquan Shaikh | a585358 | 2017-05-06 12:40:15 -0700 | [diff] [blame] | 43 | select PARALLEL_MP_AP_WORK |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 44 | select PCIEXP_ASPM |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 45 | select PCIEXP_CLK_PM |
Vadim Bendebury | 5542bb6 | 2018-02-05 19:59:09 -0800 | [diff] [blame] | 46 | select PCIEXP_COMMON_CLOCK |
Aaron Durbin | 27d153c | 2015-07-13 13:50:34 -0500 | [diff] [blame] | 47 | select PCIEXP_L1_SUB_STATE |
Subrata Banik | 93ebe49 | 2017-03-14 18:24:47 +0530 | [diff] [blame] | 48 | select PCIEX_LENGTH_64MB |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 49 | select REG_SCRIPT |
Aaron Durbin | 16246ea | 2016-08-05 21:23:37 -0500 | [diff] [blame] | 50 | select RTC |
Subrata Banik | 46a7178 | 2017-06-02 18:52:24 +0530 | [diff] [blame] | 51 | select SA_ENABLE_DPR |
Vadim Bendebury | 5542bb6 | 2018-02-05 19:59:09 -0800 | [diff] [blame] | 52 | select SMM_TSEG |
53 | select SMP | ||||
Julien Viard de Galbert | 2912e8e | 2018-08-14 16:15:26 +0200 | [diff] [blame] | 54 | select PMC_GLOBAL_RESET_ENABLE_LOCK |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 55 | select SOC_INTEL_COMMON |
Duncan Laurie | a1c8b34d | 2015-09-08 16:12:44 -0700 | [diff] [blame] | 56 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
Subrata Banik | e074d62 | 2017-02-16 16:16:37 +0530 | [diff] [blame] | 57 | select SOC_INTEL_COMMON_BLOCK |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 58 | select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG |
Barnali Sarkar | 0a203d1 | 2017-05-04 18:02:17 +0530 | [diff] [blame] | 59 | select SOC_INTEL_COMMON_BLOCK_CPU |
Barnali Sarkar | 7327386 | 2017-06-13 20:22:33 +0530 | [diff] [blame] | 60 | select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
Hannah Williams | 1760cd3 | 2017-04-06 20:54:11 -0700 | [diff] [blame] | 61 | select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS |
Vadim Bendebury | 5542bb6 | 2018-02-05 19:59:09 -0800 | [diff] [blame] | 62 | select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL |
Furquan Shaikh | 05a6f29 | 2017-03-31 14:02:47 -0700 | [diff] [blame] | 63 | select SOC_INTEL_COMMON_BLOCK_GSPI |
Subrata Banik | 93ebe49 | 2017-03-14 18:24:47 +0530 | [diff] [blame] | 64 | select SOC_INTEL_COMMON_BLOCK_SA |
Pratik Prajapati | a04aa3d | 2017-06-12 23:02:36 -0700 | [diff] [blame] | 65 | select SOC_INTEL_COMMON_BLOCK_SGX |
Subrata Banik | ece173c | 2017-12-14 18:18:34 +0530 | [diff] [blame] | 66 | select SOC_INTEL_COMMON_BLOCK_SMM |
67 | select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP | ||||
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 68 | select SOC_INTEL_COMMON_BLOCK_UART |
Matt DeVillier | 969ef10 | 2018-03-21 20:47:52 -0500 | [diff] [blame] | 69 | select SOC_INTEL_COMMON_BLOCK_VMX |
Subrata Banik | f513ceb | 2018-05-17 15:57:43 +0530 | [diff] [blame] | 70 | select SOC_INTEL_COMMON_PCH_BASE |
Aaron Durbin | c14a1a9 | 2016-06-28 15:41:07 -0500 | [diff] [blame] | 71 | select SOC_INTEL_COMMON_NHLT |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 72 | select SOC_INTEL_COMMON_RESET |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 73 | select SSE2 |
74 | select SUPPORT_CPU_UCODE_IN_CBFS | ||||
75 | select TSC_CONSTANT_RATE | ||||
Aamir Bohra | 842776e | 2017-05-25 14:12:01 +0530 | [diff] [blame] | 76 | select TSC_MONOTONIC_TIMER |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 77 | select TSC_SYNC_MFENCE |
78 | select UDELAY_TSC | ||||
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 79 | |
Arthur Heymans | 27d3f71 | 2018-01-05 17:51:46 +0100 | [diff] [blame] | 80 | config CPU_INTEL_NUM_FIT_ENTRIES |
81 | int | ||||
82 | default 10 | ||||
83 | |||||
Naresh G Solanki | fe517f6 | 2016-10-17 17:21:08 +0530 | [diff] [blame] | 84 | config MAINBOARD_USES_FSP2_0 |
85 | bool | ||||
86 | default n | ||||
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 87 | |
88 | config USE_FSP2_0_DRIVER | ||||
Nico Huber | 956cfa3 | 2017-06-28 12:20:48 +0200 | [diff] [blame] | 89 | def_bool y |
Naresh G Solanki | fe517f6 | 2016-10-17 17:21:08 +0530 | [diff] [blame] | 90 | depends on MAINBOARD_USES_FSP2_0 |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 91 | select PLATFORM_USES_FSP2_0 |
Subrata Banik | 7455881 | 2018-01-25 11:41:04 +0530 | [diff] [blame] | 92 | select UDK_2015_BINDING |
Nico Huber | 29cc331 | 2018-06-06 17:40:02 +0200 | [diff] [blame] | 93 | select INTEL_GMA_ADD_VBT if RUN_FSP_GOP |
Aaron Durbin | 79f0741 | 2017-04-16 21:49:29 -0500 | [diff] [blame] | 94 | select POSTCAR_CONSOLE |
95 | select POSTCAR_STAGE | ||||
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 96 | |
97 | config USE_FSP1_1_DRIVER | ||||
Nico Huber | 956cfa3 | 2017-06-28 12:20:48 +0200 | [diff] [blame] | 98 | def_bool y |
Naresh G Solanki | fe517f6 | 2016-10-17 17:21:08 +0530 | [diff] [blame] | 99 | depends on !MAINBOARD_USES_FSP2_0 |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 100 | select PLATFORM_USES_FSP1_1 |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 101 | select DISPLAY_FSP_ENTRY_POINTS |
102 | |||||
Furquan Shaikh | 610a33a | 2016-07-22 16:17:53 -0700 | [diff] [blame] | 103 | config CHROMEOS |
104 | select CHROMEOS_RAMOOPS_DYNAMIC | ||||
Julius Werner | 58c3938 | 2017-02-13 17:53:29 -0800 | [diff] [blame] | 105 | |
106 | config VBOOT | ||||
107 | select VBOOT_EC_SLOW_UPDATE if VBOOT_EC_SOFTWARE_SYNC | ||||
108 | select VBOOT_SEPARATE_VERSTAGE | ||||
Furquan Shaikh | 610a33a | 2016-07-22 16:17:53 -0700 | [diff] [blame] | 109 | select VBOOT_OPROM_MATTERS |
Furquan Shaikh | b8257df | 2016-07-22 09:20:56 -0700 | [diff] [blame] | 110 | select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT |
Aaron Durbin | a6914d2 | 2016-08-24 08:49:29 -0500 | [diff] [blame] | 111 | select VBOOT_STARTS_IN_BOOTBLOCK |
Furquan Shaikh | 2a12e2e | 2016-07-25 11:48:03 -0700 | [diff] [blame] | 112 | select VBOOT_VBNV_CMOS |
113 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH | ||||
Furquan Shaikh | 610a33a | 2016-07-22 16:17:53 -0700 | [diff] [blame] | 114 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 115 | config BOOTBLOCK_RESETS |
116 | string | ||||
117 | default "soc/intel/common/reset.c" | ||||
118 | |||||
Martin Roth | 59ff340 | 2016-02-09 09:06:46 -0700 | [diff] [blame] | 119 | config CBFS_SIZE |
120 | hex | ||||
121 | default 0x200000 | ||||
122 | |||||
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 123 | config CPU_ADDR_BITS |
124 | int | ||||
125 | default 36 | ||||
126 | |||||
127 | config DCACHE_RAM_BASE | ||||
Arthur Heymans | 432ac61 | 2017-06-13 14:17:05 +0200 | [diff] [blame] | 128 | hex |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 129 | default 0xfef00000 |
130 | |||||
131 | config DCACHE_RAM_SIZE | ||||
Arthur Heymans | 432ac61 | 2017-06-13 14:17:05 +0200 | [diff] [blame] | 132 | hex |
Rizwan Qureshi | 3ad6356 | 2016-08-14 15:48:33 +0530 | [diff] [blame] | 133 | default 0x40000 |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 134 | help |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 135 | The size of the cache-as-ram region required during bootblock |
136 | and/or romstage. | ||||
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 137 | |
Subrata Banik | 68d5d8b | 2016-07-18 14:13:52 +0530 | [diff] [blame] | 138 | config DCACHE_BSP_STACK_SIZE |
139 | hex | ||||
140 | default 0x4000 | ||||
141 | help | ||||
142 | The amount of anticipated stack usage in CAR by bootblock and | ||||
143 | other stages. | ||||
144 | |||||
145 | config C_ENV_BOOTBLOCK_SIZE | ||||
146 | hex | ||||
Furquan Shaikh | 7038596 | 2016-08-24 10:28:30 -0700 | [diff] [blame] | 147 | default 0xC000 |
Subrata Banik | 68d5d8b | 2016-07-18 14:13:52 +0530 | [diff] [blame] | 148 | |
Subrata Banik | 086730b | 2015-12-02 11:42:04 +0530 | [diff] [blame] | 149 | config EXCLUDE_NATIVE_SD_INTERFACE |
150 | bool | ||||
151 | default n | ||||
152 | help | ||||
153 | If you set this option to n, will not use native SD controller. | ||||
154 | |||||
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 155 | config HEAP_SIZE |
156 | hex | ||||
157 | default 0x80000 | ||||
158 | |||||
159 | config IED_REGION_SIZE | ||||
160 | hex | ||||
161 | default 0x400000 | ||||
162 | |||||
Subrata Banik | e7ceae7 | 2017-03-08 17:59:40 +0530 | [diff] [blame] | 163 | config PCR_BASE_ADDRESS |
164 | hex | ||||
165 | default 0xfd000000 | ||||
166 | help | ||||
167 | This option allows you to select MMIO Base Address of sideband bus. | ||||
168 | |||||
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 169 | config SERIAL_CPU_INIT |
170 | bool | ||||
171 | default n | ||||
172 | |||||
173 | config SERIRQ_CONTINUOUS_MODE | ||||
174 | bool | ||||
pchandri | 1d77c72 | 2015-09-09 17:22:09 -0700 | [diff] [blame] | 175 | default n |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 176 | help |
177 | If you set this option to y, the serial IRQ machine will be | ||||
178 | operated in continuous mode. | ||||
179 | |||||
180 | config SMM_RESERVED_SIZE | ||||
181 | hex | ||||
182 | default 0x200000 | ||||
183 | |||||
184 | config SMM_TSEG_SIZE | ||||
185 | hex | ||||
186 | default 0x800000 | ||||
187 | |||||
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 188 | config VGA_BIOS_ID |
189 | string | ||||
190 | default "8086,0406" | ||||
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 191 | |
Aaron Durbin | e33a172 | 2015-07-30 16:52:56 -0500 | [diff] [blame] | 192 | config UART_DEBUG |
193 | bool "Enable UART debug port." | ||||
Aaron Durbin | e33a172 | 2015-07-30 16:52:56 -0500 | [diff] [blame] | 194 | default n |
Martin Roth | 1afcb23 | 2015-08-15 17:36:15 -0600 | [diff] [blame] | 195 | select CONSOLE_SERIAL |
Aaron Durbin | e33a172 | 2015-07-30 16:52:56 -0500 | [diff] [blame] | 196 | select DRIVERS_UART |
Aaron Durbin | e33a172 | 2015-07-30 16:52:56 -0500 | [diff] [blame] | 197 | select DRIVERS_UART_8250MEM_32 |
Furquan Shaikh | b168db7 | 2016-08-01 19:37:38 -0700 | [diff] [blame] | 198 | select NO_UART_ON_SUPERIO |
Aaron Durbin | e33a172 | 2015-07-30 16:52:56 -0500 | [diff] [blame] | 199 | |
Subrata Banik | 19a7ade | 2017-08-14 11:55:10 +0530 | [diff] [blame] | 200 | config UART_FOR_CONSOLE |
201 | int "Index for LPSS UART port to use for console" | ||||
202 | default 2 if DRIVERS_UART_8250MEM | ||||
Subrata Banik | b045d4c | 2017-08-30 11:47:32 +0530 | [diff] [blame] | 203 | default 0 |
Subrata Banik | 19a7ade | 2017-08-14 11:55:10 +0530 | [diff] [blame] | 204 | help |
205 | Index for LPSS UART port to use for console: | ||||
206 | 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2 | ||||
207 | |||||
Teo Boon Tiong | 2fc06c8 | 2016-09-15 11:11:45 +0800 | [diff] [blame] | 208 | config SKYLAKE_SOC_PCH_H |
209 | bool | ||||
210 | default n | ||||
211 | help | ||||
212 | Choose this option if you have a PCH-H chipset. | ||||
213 | |||||
Aaron Durbin | 3953e39 | 2015-09-03 00:41:29 -0500 | [diff] [blame] | 214 | config CHIPSET_BOOTBLOCK_INCLUDE |
215 | string | ||||
216 | default "soc/intel/skylake/bootblock/timestamp.inc" | ||||
217 | |||||
Aaron Durbin | ed8a723 | 2015-11-24 12:35:06 -0600 | [diff] [blame] | 218 | config NHLT_DMIC_2CH |
219 | bool | ||||
220 | default n | ||||
221 | help | ||||
222 | Include DSP firmware settings for 2 channel DMIC array. | ||||
223 | |||||
224 | config NHLT_DMIC_4CH | ||||
225 | bool | ||||
226 | default n | ||||
227 | help | ||||
228 | Include DSP firmware settings for 4 channel DMIC array. | ||||
229 | |||||
230 | config NHLT_NAU88L25 | ||||
231 | bool | ||||
232 | default n | ||||
233 | help | ||||
234 | Include DSP firmware settings for nau88l25 headset codec. | ||||
235 | |||||
236 | config NHLT_MAX98357 | ||||
237 | bool | ||||
238 | default n | ||||
239 | help | ||||
240 | Include DSP firmware settings for max98357 amplifier. | ||||
241 | |||||
Duncan Laurie | e6c8a38 | 2018-03-26 02:45:02 -0700 | [diff] [blame] | 242 | config NHLT_MAX98373 |
243 | bool | ||||
244 | default n | ||||
245 | help | ||||
246 | Include DSP firmware settings for max98373 amplifier. | ||||
247 | |||||
Aaron Durbin | ed8a723 | 2015-11-24 12:35:06 -0600 | [diff] [blame] | 248 | config NHLT_SSM4567 |
249 | bool | ||||
250 | default n | ||||
251 | help | ||||
252 | Include DSP firmware settings for ssm4567 smart amplifier. | ||||
253 | |||||
Duncan Laurie | 4a75a66 | 2017-03-02 10:13:51 -0800 | [diff] [blame] | 254 | config NHLT_RT5514 |
255 | bool | ||||
256 | default n | ||||
257 | help | ||||
258 | Include DSP firmware settings for rt5514 DSP. | ||||
259 | |||||
Rizwan Qureshi | 17335fa | 2017-01-14 06:08:21 +0530 | [diff] [blame] | 260 | config NHLT_RT5663 |
261 | bool | ||||
262 | default n | ||||
263 | help | ||||
264 | Include DSP firmware settings for rt5663 headset codec. | ||||
265 | |||||
266 | config NHLT_MAX98927 | ||||
267 | bool | ||||
268 | default n | ||||
269 | help | ||||
270 | Include DSP firmware settings for max98927 amplifier. | ||||
271 | |||||
Naveen Manohar | 83670c5 | 2017-11-04 02:55:09 +0530 | [diff] [blame] | 272 | config NHLT_DA7219 |
273 | bool | ||||
274 | default n | ||||
275 | help | ||||
276 | Include DSP firmware settings for DA7219 headset codec. | ||||
277 | |||||
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 278 | choice |
279 | prompt "Cache-as-ram implementation" | ||||
Subrata Banik | 9e3ba21 | 2018-01-08 15:28:26 +0530 | [diff] [blame] | 280 | default USE_SKYLAKE_CAR_NEM_ENHANCED |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 281 | help |
282 | This option allows you to select how cache-as-ram (CAR) is set up. | ||||
283 | |||||
Subrata Banik | 9e3ba21 | 2018-01-08 15:28:26 +0530 | [diff] [blame] | 284 | config USE_SKYLAKE_CAR_NEM_ENHANCED |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 285 | bool "Enhanced Non-evict mode" |
286 | select SOC_INTEL_COMMON_BLOCK_CAR | ||||
287 | select INTEL_CAR_NEM_ENHANCED | ||||
288 | help | ||||
Subrata Banik | 9e3ba21 | 2018-01-08 15:28:26 +0530 | [diff] [blame] | 289 | A current limitation of NEM (Non-Evict mode) is that code and data |
290 | sizes are derived from the requirement to not write out any modified | ||||
291 | cache line. With NEM, if there is no physical memory behind the | ||||
292 | cached area, the modified data will be lost and NEM results will be | ||||
293 | inconsistent. ENHANCED NEM guarantees that modified data is always | ||||
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 294 | kept in cache while clean data is replaced. |
295 | |||||
296 | config USE_SKYLAKE_FSP_CAR | ||||
297 | bool "Use FSP CAR" | ||||
298 | select FSP_CAR | ||||
299 | help | ||||
Subrata Banik | 9e3ba21 | 2018-01-08 15:28:26 +0530 | [diff] [blame] | 300 | Use FSP APIs to initialize and tear down the Cache-As-Ram. |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 301 | |
302 | endchoice | ||||
303 | |||||
Subrata Banik | fbdc719 | 2016-01-19 19:19:15 +0530 | [diff] [blame] | 304 | config SKIP_FSP_CAR |
Martin Roth | b00ddec | 2016-01-31 10:39:47 -0700 | [diff] [blame] | 305 | bool "Skip cache as RAM setup in FSP" |
306 | default y | ||||
307 | help | ||||
308 | Skip Cache as RAM setup in FSP. | ||||
Subrata Banik | fbdc719 | 2016-01-19 19:19:15 +0530 | [diff] [blame] | 309 | |
Aaron Durbin | e56191e | 2016-08-11 09:50:49 -0500 | [diff] [blame] | 310 | config SPI_FLASH_INCLUDE_ALL_DRIVERS |
311 | bool | ||||
312 | default n | ||||
313 | |||||
Rizwan Qureshi | d8bb69a | 2016-11-08 21:01:09 +0530 | [diff] [blame] | 314 | config MAX_ROOT_PORTS |
315 | int | ||||
316 | default 24 if PLATFORM_USES_FSP2_0 | ||||
317 | default 20 if PLATFORM_USES_FSP1_1 | ||||
318 | |||||
Jenny TC | 2864f85 | 2017-02-09 16:01:59 +0530 | [diff] [blame] | 319 | config NO_FADT_8042 |
320 | bool | ||||
321 | default n | ||||
322 | help | ||||
323 | Choose this option if you want to disable 8042 Keyboard | ||||
324 | |||||
Aaron Durbin | 551e4be | 2018-04-10 09:24:54 -0600 | [diff] [blame] | 325 | config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
Furquan Shaikh | 340908a | 2017-04-04 11:47:19 -0700 | [diff] [blame] | 326 | int |
327 | default 120 | ||||
328 | |||||
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 329 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
330 | int | ||||
Aaron Durbin | 551e4be | 2018-04-10 09:24:54 -0600 | [diff] [blame] | 331 | default SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 332 | |
Furquan Shaikh | 05a6f29 | 2017-03-31 14:02:47 -0700 | [diff] [blame] | 333 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
334 | int | ||||
335 | default 2 | ||||
336 | |||||
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 337 | config SOC_INTEL_I2C_DEV_MAX |
338 | int | ||||
339 | default 6 | ||||
340 | |||||
Aamir Bohra | 1041d39 | 2017-06-02 11:56:14 +0530 | [diff] [blame] | 341 | config CPU_BCLK_MHZ |
342 | int | ||||
343 | default 100 | ||||
344 | |||||
Furquan Shaikh | 3406dd6 | 2017-08-04 15:58:26 -0700 | [diff] [blame] | 345 | # Clock divider parameters for 115200 baud rate |
346 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL | ||||
347 | hex | ||||
348 | default 0x30 | ||||
349 | |||||
350 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL | ||||
351 | hex | ||||
352 | default 0xc35 | ||||
353 | |||||
Furquan Shaikh | a3ad990 | 2018-03-21 10:45:08 -0700 | [diff] [blame] | 354 | config IFD_CHIPSET |
355 | string | ||||
356 | default "sklkbl" | ||||
357 | |||||
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 358 | endif |