Elyes HAOUAS | 36787b0 | 2020-05-07 12:07:24 +0200 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 2 | |
| 3 | config NORTHBRIDGE_INTEL_HASWELL |
| 4 | bool |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 5 | select CPU_INTEL_HASWELL |
Arthur Heymans | f300f36 | 2018-01-27 13:39:12 +0100 | [diff] [blame] | 6 | select CACHE_MRC_SETTINGS |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 7 | select INTEL_DDI |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 8 | select INTEL_GMA_ACPI |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 9 | |
| 10 | if NORTHBRIDGE_INTEL_HASWELL |
| 11 | |
Angel Pons | 9fdd557 | 2022-05-06 21:12:14 +0200 | [diff] [blame] | 12 | config USE_NATIVE_RAMINIT |
| 13 | bool "[NOT WORKING] Use native raminit" |
| 14 | default n |
| 15 | select HAVE_DEBUG_RAM_SETUP |
| 16 | help |
| 17 | Select if you want to use coreboot implementation of raminit rather than |
| 18 | MRC.bin. Currently incomplete and does not boot. |
| 19 | |
Arthur Heymans | 77d5e74 | 2019-01-03 21:11:45 +0100 | [diff] [blame] | 20 | config HASWELL_VBOOT_IN_BOOTBLOCK |
| 21 | depends on VBOOT |
| 22 | bool "Start verstage in bootblock" |
| 23 | default y |
| 24 | select VBOOT_STARTS_IN_BOOTBLOCK |
Arthur Heymans | 77d5e74 | 2019-01-03 21:11:45 +0100 | [diff] [blame] | 25 | help |
| 26 | Haswell can either start verstage in a separate stage |
| 27 | right after the bootblock has run or it can start it |
| 28 | after romstage for compatibility reasons. |
Joel Kitching | 82d73e2 | 2019-04-30 13:13:40 +0800 | [diff] [blame] | 29 | Haswell however uses a mrc.bin to initialize memory which |
Arthur Heymans | 77d5e74 | 2019-01-03 21:11:45 +0100 | [diff] [blame] | 30 | needs to be located at a fixed offset. Therefore even with |
| 31 | a separate verstage starting after the bootblock that same |
| 32 | binary is used meaning a jump is made from RW to the RO region |
| 33 | and back to the RW region after the binary is done. |
| 34 | |
Julius Werner | 1210b41 | 2017-03-27 19:26:32 -0700 | [diff] [blame] | 35 | config VBOOT |
Joel Kitching | 6672bd8 | 2019-04-10 16:06:21 +0800 | [diff] [blame] | 36 | select VBOOT_MUST_REQUEST_DISPLAY |
Arthur Heymans | 77d5e74 | 2019-01-03 21:11:45 +0100 | [diff] [blame] | 37 | select VBOOT_STARTS_IN_ROMSTAGE if !HASWELL_VBOOT_IN_BOOTBLOCK |
Julius Werner | 1210b41 | 2017-03-27 19:26:32 -0700 | [diff] [blame] | 38 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 39 | config VGA_BIOS_ID |
| 40 | string |
| 41 | default "8086,0166" |
| 42 | |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 43 | config ECAM_MMCONF_BASE_ADDRESS |
Elyes HAOUAS | ef169d6 | 2018-09-14 10:28:52 +0200 | [diff] [blame] | 44 | default 0xf0000000 |
| 45 | |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 46 | config ECAM_MMCONF_BUS_NUMBER |
Angel Pons | 32770f8 | 2021-01-20 15:03:30 +0100 | [diff] [blame] | 47 | int |
| 48 | default 64 |
| 49 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 50 | config DCACHE_RAM_BASE |
| 51 | hex |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 52 | default 0xff7c0000 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 53 | |
| 54 | config DCACHE_RAM_SIZE |
| 55 | hex |
Angel Pons | 9fdd557 | 2022-05-06 21:12:14 +0200 | [diff] [blame] | 56 | default 0x40000 if USE_NATIVE_RAMINIT |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 57 | default 0x10000 |
| 58 | help |
| 59 | The size of the cache-as-ram region required during bootblock |
| 60 | and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE |
| 61 | must add up to a power of 2. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 62 | |
| 63 | config DCACHE_RAM_MRC_VAR_SIZE |
| 64 | hex |
Angel Pons | 9fdd557 | 2022-05-06 21:12:14 +0200 | [diff] [blame] | 65 | default 0x0 if USE_NATIVE_RAMINIT |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 66 | default 0x30000 |
| 67 | help |
| 68 | The amount of cache-as-ram region required by the reference code. |
| 69 | |
Arthur Heymans | 8e646e7 | 2018-06-05 11:19:22 +0200 | [diff] [blame] | 70 | config DCACHE_BSP_STACK_SIZE |
| 71 | hex |
Angel Pons | 9fdd557 | 2022-05-06 21:12:14 +0200 | [diff] [blame] | 72 | default 0x20000 if USE_NATIVE_RAMINIT |
Arthur Heymans | 8e646e7 | 2018-06-05 11:19:22 +0200 | [diff] [blame] | 73 | default 0x2000 |
| 74 | help |
| 75 | The amount of anticipated stack usage in CAR by bootblock and |
| 76 | other stages. |
| 77 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 78 | config HAVE_MRC |
| 79 | bool "Add a System Agent binary" |
Angel Pons | 9fdd557 | 2022-05-06 21:12:14 +0200 | [diff] [blame] | 80 | depends on !USE_NATIVE_RAMINIT |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 81 | help |
| 82 | Select this option to add a System Agent binary to |
| 83 | the resulting coreboot image. |
| 84 | |
| 85 | Note: Without this binary coreboot will not work |
| 86 | |
| 87 | config MRC_FILE |
| 88 | string "Intel System Agent path and filename" |
| 89 | depends on HAVE_MRC |
| 90 | default "mrc.bin" |
| 91 | help |
| 92 | The path and filename of the file to use as System Agent |
| 93 | binary. |
| 94 | |
Angel Pons | 84641c8 | 2020-08-29 02:52:09 +0200 | [diff] [blame] | 95 | config HASWELL_HIDE_PEG_FROM_MRC |
| 96 | bool "Hide PEG devices from MRC to work around hardcoded MRC behavior" |
Angel Pons | 9fdd557 | 2022-05-06 21:12:14 +0200 | [diff] [blame] | 97 | depends on !USE_NATIVE_RAMINIT |
Angel Pons | 84641c8 | 2020-08-29 02:52:09 +0200 | [diff] [blame] | 98 | default y |
| 99 | help |
| 100 | If set, hides all PEG devices from MRC. This allows the iGPU |
| 101 | to be used even when a dedicated graphics card is present. |
| 102 | However, it prevents MRC from programming PEG AFE registers, |
| 103 | which can make PEG devices unstable. When unsure, choose N. |
| 104 | |
Arthur Heymans | 77d5e74 | 2019-01-03 21:11:45 +0100 | [diff] [blame] | 105 | # The UEFI System Agent binary needs to be at a fixed offset in the flash |
| 106 | # and can therefore only reside in the COREBOOT fmap region |
| 107 | config RO_REGION_ONLY |
| 108 | string |
| 109 | depends on VBOOT |
| 110 | default "mrc.bin" |
| 111 | |
Nico Huber | 612a867 | 2019-02-19 19:11:29 +0100 | [diff] [blame] | 112 | config INTEL_GMA_BCLV_OFFSET |
| 113 | default 0x48254 |
| 114 | |
Angel Pons | 1be9f58 | 2020-07-03 21:31:17 +0200 | [diff] [blame] | 115 | config ENABLE_DDR_2X_REFRESH |
| 116 | bool "Enable DRAM Refresh 2x support" |
| 117 | default n |
| 118 | help |
| 119 | When enabled, the memory controller will refresh the DRAM twice as often. |
| 120 | This probably only happens when the DRAM gets hot, but what MRC exactly |
| 121 | does when this setting is enabled has not been investigated. |
| 122 | |
Angel Pons | f95b9b4 | 2021-01-20 01:10:48 +0100 | [diff] [blame] | 123 | config FIXED_MCHBAR_MMIO_BASE |
| 124 | default 0xfed10000 |
| 125 | |
| 126 | config FIXED_DMIBAR_MMIO_BASE |
| 127 | default 0xfed18000 |
| 128 | |
| 129 | config FIXED_EPBAR_MMIO_BASE |
| 130 | default 0xfed19000 |
| 131 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 132 | endif |