blob: 48a92b6d74bd3695abc9c5c393603efc31ff533e [file] [log] [blame]
Aaron Durbin76c37002012-10-30 09:03:43 -05001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2010 Google Inc.
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
Aaron Durbin76c37002012-10-30 09:03:43 -050015
16config NORTHBRIDGE_INTEL_HASWELL
17 bool
Aaron Durbin76c37002012-10-30 09:03:43 -050018 select CPU_INTEL_HASWELL
Alexander Couzens92fc0722016-03-09 14:36:46 +010019 select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE
Furquan Shaikh77f48cd2013-08-19 10:16:50 -070020 select INTEL_DDI
21 select INTEL_DP
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +010022 select INTEL_GMA_ACPI
Arthur Heymans410f2562017-01-25 15:27:52 +010023 select RELOCATABLE_RAMSTAGE
24 select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
Aaron Durbin76c37002012-10-30 09:03:43 -050025
26if NORTHBRIDGE_INTEL_HASWELL
27
Julius Werner1210b412017-03-27 19:26:32 -070028config VBOOT
29 select VBOOT_STARTS_IN_ROMSTAGE
30
Aaron Durbin6d04f0f2012-10-31 22:57:16 -050031config BOOTBLOCK_NORTHBRIDGE_INIT
32 string
33 default "northbridge/intel/haswell/bootblock.c"
34
Aaron Durbin76c37002012-10-30 09:03:43 -050035config VGA_BIOS_ID
36 string
37 default "8086,0166"
38
Aaron Durbin76c37002012-10-30 09:03:43 -050039config CACHE_MRC_SIZE_KB
40 int
41 default 512
42
Aaron Durbin76c37002012-10-30 09:03:43 -050043config MRC_CACHE_SIZE
44 hex
45 depends on !CHROMEOS
46 default 0x10000
47
48config DCACHE_RAM_BASE
49 hex
Aaron Durbin3d0071b2013-01-18 14:32:50 -060050 default 0xff7c0000
Aaron Durbin76c37002012-10-30 09:03:43 -050051
52config DCACHE_RAM_SIZE
53 hex
Aaron Durbin3d0071b2013-01-18 14:32:50 -060054 default 0x10000
55 help
56 The size of the cache-as-ram region required during bootblock
57 and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
58 must add up to a power of 2.
Aaron Durbin76c37002012-10-30 09:03:43 -050059
60config DCACHE_RAM_MRC_VAR_SIZE
61 hex
Aaron Durbin3d0071b2013-01-18 14:32:50 -060062 default 0x30000
63 help
64 The amount of cache-as-ram region required by the reference code.
65
66config DCACHE_RAM_ROMSTAGE_STACK_SIZE
67 hex
68 default 0x2000
69 help
70 The amount of anticipated stack usage from the data cache
Elyes HAOUAS15279a92016-07-28 21:05:26 +020071 during pre-ram ROM stage execution.
Aaron Durbin76c37002012-10-30 09:03:43 -050072
Aaron Durbin76c37002012-10-30 09:03:43 -050073config HAVE_MRC
74 bool "Add a System Agent binary"
75 help
76 Select this option to add a System Agent binary to
77 the resulting coreboot image.
78
79 Note: Without this binary coreboot will not work
80
81config MRC_FILE
82 string "Intel System Agent path and filename"
83 depends on HAVE_MRC
84 default "mrc.bin"
85 help
86 The path and filename of the file to use as System Agent
87 binary.
88
Stefan Reinauerf1aabec2014-01-22 15:16:30 -080089config PRE_GRAPHICS_DELAY
Stefan Reinauer7034b9e2014-02-11 16:18:07 -080090 int "Graphics initialization delay in ms"
Stefan Reinauerf1aabec2014-01-22 15:16:30 -080091 default 0
92 help
93 On some systems, coreboot boots so fast that connected monitors
94 (mostly TVs) won't be able to wake up fast enough to talk to the
95 VBIOS. On those systems we need to wait for a bit before executing
96 the VBIOS.
97
Aaron Durbin76c37002012-10-30 09:03:43 -050098endif