blob: 0362ffee513cfec42825c5ca5c98709fc967bbb1 [file] [log] [blame]
Aaron Durbin76c37002012-10-30 09:03:43 -05001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2010 Google Inc.
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
Aaron Durbin76c37002012-10-30 09:03:43 -050015
16config NORTHBRIDGE_INTEL_HASWELL
17 bool
Aaron Durbin76c37002012-10-30 09:03:43 -050018 select CPU_INTEL_HASWELL
Arthur Heymansf300f362018-01-27 13:39:12 +010019 select CACHE_MRC_SETTINGS
Furquan Shaikh77f48cd2013-08-19 10:16:50 -070020 select INTEL_DDI
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +010021 select INTEL_GMA_ACPI
Arthur Heymans410f2562017-01-25 15:27:52 +010022 select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
Arthur Heymans88af0f32018-06-03 12:37:54 +020023 select POSTCAR_STAGE
24 select POSTCAR_CONSOLE
Aaron Durbin76c37002012-10-30 09:03:43 -050025
26if NORTHBRIDGE_INTEL_HASWELL
27
Julius Werner1210b412017-03-27 19:26:32 -070028config VBOOT
29 select VBOOT_STARTS_IN_ROMSTAGE
30
Aaron Durbin6d04f0f2012-10-31 22:57:16 -050031config BOOTBLOCK_NORTHBRIDGE_INIT
32 string
33 default "northbridge/intel/haswell/bootblock.c"
34
Aaron Durbin76c37002012-10-30 09:03:43 -050035config VGA_BIOS_ID
36 string
37 default "8086,0166"
38
Elyes HAOUASef169d62018-09-14 10:28:52 +020039config MMCONF_BASE_ADDRESS
40 hex
41 default 0xf0000000
42
Aaron Durbin76c37002012-10-30 09:03:43 -050043config CACHE_MRC_SIZE_KB
44 int
45 default 512
46
Aaron Durbin76c37002012-10-30 09:03:43 -050047config DCACHE_RAM_BASE
48 hex
Aaron Durbin3d0071b2013-01-18 14:32:50 -060049 default 0xff7c0000
Aaron Durbin76c37002012-10-30 09:03:43 -050050
51config DCACHE_RAM_SIZE
52 hex
Aaron Durbin3d0071b2013-01-18 14:32:50 -060053 default 0x10000
54 help
55 The size of the cache-as-ram region required during bootblock
56 and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
57 must add up to a power of 2.
Aaron Durbin76c37002012-10-30 09:03:43 -050058
59config DCACHE_RAM_MRC_VAR_SIZE
60 hex
Aaron Durbin3d0071b2013-01-18 14:32:50 -060061 default 0x30000
62 help
63 The amount of cache-as-ram region required by the reference code.
64
Aaron Durbin76c37002012-10-30 09:03:43 -050065config HAVE_MRC
66 bool "Add a System Agent binary"
67 help
68 Select this option to add a System Agent binary to
69 the resulting coreboot image.
70
71 Note: Without this binary coreboot will not work
72
73config MRC_FILE
74 string "Intel System Agent path and filename"
75 depends on HAVE_MRC
76 default "mrc.bin"
77 help
78 The path and filename of the file to use as System Agent
79 binary.
80
Stefan Reinauerf1aabec2014-01-22 15:16:30 -080081config PRE_GRAPHICS_DELAY
Stefan Reinauer7034b9e2014-02-11 16:18:07 -080082 int "Graphics initialization delay in ms"
Stefan Reinauerf1aabec2014-01-22 15:16:30 -080083 default 0
84 help
85 On some systems, coreboot boots so fast that connected monitors
86 (mostly TVs) won't be able to wake up fast enough to talk to the
87 VBIOS. On those systems we need to wait for a bit before executing
88 the VBIOS.
89
Aaron Durbin76c37002012-10-30 09:03:43 -050090endif