Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2010 Google Inc. |
| 5 | ## |
| 6 | ## This program is free software; you can redistribute it and/or modify |
| 7 | ## it under the terms of the GNU General Public License as published by |
| 8 | ## the Free Software Foundation; version 2 of the License. |
| 9 | ## |
| 10 | ## This program is distributed in the hope that it will be useful, |
| 11 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | ## GNU General Public License for more details. |
| 14 | ## |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 15 | |
| 16 | config NORTHBRIDGE_INTEL_HASWELL |
| 17 | bool |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 18 | select CPU_INTEL_HASWELL |
Arthur Heymans | f300f36 | 2018-01-27 13:39:12 +0100 | [diff] [blame] | 19 | select CACHE_MRC_SETTINGS |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 20 | select INTEL_DDI |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 21 | select INTEL_GMA_ACPI |
Arthur Heymans | 410f256 | 2017-01-25 15:27:52 +0100 | [diff] [blame] | 22 | select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM |
Arthur Heymans | 88af0f3 | 2018-06-03 12:37:54 +0200 | [diff] [blame] | 23 | select POSTCAR_STAGE |
| 24 | select POSTCAR_CONSOLE |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 25 | |
| 26 | if NORTHBRIDGE_INTEL_HASWELL |
| 27 | |
Julius Werner | 1210b41 | 2017-03-27 19:26:32 -0700 | [diff] [blame] | 28 | config VBOOT |
| 29 | select VBOOT_STARTS_IN_ROMSTAGE |
| 30 | |
Aaron Durbin | 6d04f0f | 2012-10-31 22:57:16 -0500 | [diff] [blame] | 31 | config BOOTBLOCK_NORTHBRIDGE_INIT |
| 32 | string |
| 33 | default "northbridge/intel/haswell/bootblock.c" |
| 34 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 35 | config VGA_BIOS_ID |
| 36 | string |
| 37 | default "8086,0166" |
| 38 | |
Elyes HAOUAS | ef169d6 | 2018-09-14 10:28:52 +0200 | [diff] [blame^] | 39 | config MMCONF_BASE_ADDRESS |
| 40 | hex |
| 41 | default 0xf0000000 |
| 42 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 43 | config CACHE_MRC_SIZE_KB |
| 44 | int |
| 45 | default 512 |
| 46 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 47 | config DCACHE_RAM_BASE |
| 48 | hex |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 49 | default 0xff7c0000 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 50 | |
| 51 | config DCACHE_RAM_SIZE |
| 52 | hex |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 53 | default 0x10000 |
| 54 | help |
| 55 | The size of the cache-as-ram region required during bootblock |
| 56 | and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE |
| 57 | must add up to a power of 2. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 58 | |
| 59 | config DCACHE_RAM_MRC_VAR_SIZE |
| 60 | hex |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 61 | default 0x30000 |
| 62 | help |
| 63 | The amount of cache-as-ram region required by the reference code. |
| 64 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 65 | config HAVE_MRC |
| 66 | bool "Add a System Agent binary" |
| 67 | help |
| 68 | Select this option to add a System Agent binary to |
| 69 | the resulting coreboot image. |
| 70 | |
| 71 | Note: Without this binary coreboot will not work |
| 72 | |
| 73 | config MRC_FILE |
| 74 | string "Intel System Agent path and filename" |
| 75 | depends on HAVE_MRC |
| 76 | default "mrc.bin" |
| 77 | help |
| 78 | The path and filename of the file to use as System Agent |
| 79 | binary. |
| 80 | |
Stefan Reinauer | f1aabec | 2014-01-22 15:16:30 -0800 | [diff] [blame] | 81 | config PRE_GRAPHICS_DELAY |
Stefan Reinauer | 7034b9e | 2014-02-11 16:18:07 -0800 | [diff] [blame] | 82 | int "Graphics initialization delay in ms" |
Stefan Reinauer | f1aabec | 2014-01-22 15:16:30 -0800 | [diff] [blame] | 83 | default 0 |
| 84 | help |
| 85 | On some systems, coreboot boots so fast that connected monitors |
| 86 | (mostly TVs) won't be able to wake up fast enough to talk to the |
| 87 | VBIOS. On those systems we need to wait for a bit before executing |
| 88 | the VBIOS. |
| 89 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 90 | endif |