blob: 242ab18c4984d8795ed4e192415d1a974750859f [file] [log] [blame]
Aaron Durbin76c37002012-10-30 09:03:43 -05001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2010 Google Inc.
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
Aaron Durbin76c37002012-10-30 09:03:43 -050015
16config NORTHBRIDGE_INTEL_HASWELL
17 bool
Aaron Durbin76c37002012-10-30 09:03:43 -050018 select CPU_INTEL_HASWELL
Arthur Heymansf300f362018-01-27 13:39:12 +010019 select CACHE_MRC_SETTINGS
Furquan Shaikh77f48cd2013-08-19 10:16:50 -070020 select INTEL_DDI
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +010021 select INTEL_GMA_ACPI
Arthur Heymans410f2562017-01-25 15:27:52 +010022 select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
Arthur Heymans88af0f32018-06-03 12:37:54 +020023 select POSTCAR_STAGE
24 select POSTCAR_CONSOLE
Arthur Heymans8e646e72018-06-05 11:19:22 +020025 select C_ENVIRONMENT_BOOTBLOCK
26# select BOOTBLOCK_CONSOLE TODO: route LPC
Aaron Durbin76c37002012-10-30 09:03:43 -050027
28if NORTHBRIDGE_INTEL_HASWELL
29
Julius Werner1210b412017-03-27 19:26:32 -070030config VBOOT
Julius Werner9993b6f2019-03-28 18:01:26 -070031 select VBOOT_OPROM_MATTERS
Julius Werner1210b412017-03-27 19:26:32 -070032 select VBOOT_STARTS_IN_ROMSTAGE
33
Aaron Durbin76c37002012-10-30 09:03:43 -050034config VGA_BIOS_ID
35 string
36 default "8086,0166"
37
Elyes HAOUASef169d62018-09-14 10:28:52 +020038config MMCONF_BASE_ADDRESS
39 hex
40 default 0xf0000000
41
Aaron Durbin76c37002012-10-30 09:03:43 -050042config CACHE_MRC_SIZE_KB
43 int
44 default 512
45
Aaron Durbin76c37002012-10-30 09:03:43 -050046config DCACHE_RAM_BASE
47 hex
Aaron Durbin3d0071b2013-01-18 14:32:50 -060048 default 0xff7c0000
Aaron Durbin76c37002012-10-30 09:03:43 -050049
50config DCACHE_RAM_SIZE
51 hex
Aaron Durbin3d0071b2013-01-18 14:32:50 -060052 default 0x10000
53 help
54 The size of the cache-as-ram region required during bootblock
55 and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
56 must add up to a power of 2.
Aaron Durbin76c37002012-10-30 09:03:43 -050057
58config DCACHE_RAM_MRC_VAR_SIZE
59 hex
Aaron Durbin3d0071b2013-01-18 14:32:50 -060060 default 0x30000
61 help
62 The amount of cache-as-ram region required by the reference code.
63
Arthur Heymans8e646e72018-06-05 11:19:22 +020064config DCACHE_BSP_STACK_SIZE
65 hex
66 default 0x2000
67 help
68 The amount of anticipated stack usage in CAR by bootblock and
69 other stages.
70
Aaron Durbin76c37002012-10-30 09:03:43 -050071config HAVE_MRC
72 bool "Add a System Agent binary"
73 help
74 Select this option to add a System Agent binary to
75 the resulting coreboot image.
76
77 Note: Without this binary coreboot will not work
78
79config MRC_FILE
80 string "Intel System Agent path and filename"
81 depends on HAVE_MRC
82 default "mrc.bin"
83 help
84 The path and filename of the file to use as System Agent
85 binary.
86
Stefan Reinauerf1aabec2014-01-22 15:16:30 -080087config PRE_GRAPHICS_DELAY
Stefan Reinauer7034b9e2014-02-11 16:18:07 -080088 int "Graphics initialization delay in ms"
Stefan Reinauerf1aabec2014-01-22 15:16:30 -080089 default 0
90 help
91 On some systems, coreboot boots so fast that connected monitors
92 (mostly TVs) won't be able to wake up fast enough to talk to the
93 VBIOS. On those systems we need to wait for a bit before executing
94 the VBIOS.
95
Aaron Durbin76c37002012-10-30 09:03:43 -050096endif