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Elyes HAOUAS36787b02020-05-07 12:07:24 +02001# SPDX-License-Identifier: GPL-2.0-only
Aaron Durbin76c37002012-10-30 09:03:43 -05002
3config NORTHBRIDGE_INTEL_HASWELL
4 bool
Aaron Durbin76c37002012-10-30 09:03:43 -05005 select CPU_INTEL_HASWELL
Arthur Heymansf300f362018-01-27 13:39:12 +01006 select CACHE_MRC_SETTINGS
Furquan Shaikh77f48cd2013-08-19 10:16:50 -07007 select INTEL_DDI
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +01008 select INTEL_GMA_ACPI
Aaron Durbin76c37002012-10-30 09:03:43 -05009
10if NORTHBRIDGE_INTEL_HASWELL
11
Arthur Heymans77d5e742019-01-03 21:11:45 +010012config HASWELL_VBOOT_IN_BOOTBLOCK
13 depends on VBOOT
14 bool "Start verstage in bootblock"
15 default y
16 select VBOOT_STARTS_IN_BOOTBLOCK
Arthur Heymans77d5e742019-01-03 21:11:45 +010017 help
18 Haswell can either start verstage in a separate stage
19 right after the bootblock has run or it can start it
20 after romstage for compatibility reasons.
Joel Kitching82d73e22019-04-30 13:13:40 +080021 Haswell however uses a mrc.bin to initialize memory which
Arthur Heymans77d5e742019-01-03 21:11:45 +010022 needs to be located at a fixed offset. Therefore even with
23 a separate verstage starting after the bootblock that same
24 binary is used meaning a jump is made from RW to the RO region
25 and back to the RW region after the binary is done.
26
Julius Werner1210b412017-03-27 19:26:32 -070027config VBOOT
Joel Kitching6672bd82019-04-10 16:06:21 +080028 select VBOOT_MUST_REQUEST_DISPLAY
Arthur Heymans77d5e742019-01-03 21:11:45 +010029 select VBOOT_STARTS_IN_ROMSTAGE if !HASWELL_VBOOT_IN_BOOTBLOCK
Julius Werner1210b412017-03-27 19:26:32 -070030
Aaron Durbin76c37002012-10-30 09:03:43 -050031config VGA_BIOS_ID
32 string
33 default "8086,0166"
34
Shelley Chen4e9bb332021-10-20 15:43:45 -070035config ECAM_MMCONF_BASE_ADDRESS
Elyes HAOUASef169d62018-09-14 10:28:52 +020036 default 0xf0000000
37
Shelley Chen4e9bb332021-10-20 15:43:45 -070038config ECAM_MMCONF_BUS_NUMBER
Angel Pons32770f82021-01-20 15:03:30 +010039 int
40 default 64
41
Aaron Durbin76c37002012-10-30 09:03:43 -050042config DCACHE_RAM_BASE
43 hex
Aaron Durbin3d0071b2013-01-18 14:32:50 -060044 default 0xff7c0000
Aaron Durbin76c37002012-10-30 09:03:43 -050045
46config DCACHE_RAM_SIZE
47 hex
Aaron Durbin3d0071b2013-01-18 14:32:50 -060048 default 0x10000
49 help
50 The size of the cache-as-ram region required during bootblock
51 and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
52 must add up to a power of 2.
Aaron Durbin76c37002012-10-30 09:03:43 -050053
54config DCACHE_RAM_MRC_VAR_SIZE
55 hex
Aaron Durbin3d0071b2013-01-18 14:32:50 -060056 default 0x30000
57 help
58 The amount of cache-as-ram region required by the reference code.
59
Arthur Heymans8e646e72018-06-05 11:19:22 +020060config DCACHE_BSP_STACK_SIZE
61 hex
62 default 0x2000
63 help
64 The amount of anticipated stack usage in CAR by bootblock and
65 other stages.
66
Aaron Durbin76c37002012-10-30 09:03:43 -050067config HAVE_MRC
68 bool "Add a System Agent binary"
69 help
70 Select this option to add a System Agent binary to
71 the resulting coreboot image.
72
73 Note: Without this binary coreboot will not work
74
75config MRC_FILE
76 string "Intel System Agent path and filename"
77 depends on HAVE_MRC
78 default "mrc.bin"
79 help
80 The path and filename of the file to use as System Agent
81 binary.
82
Angel Pons84641c82020-08-29 02:52:09 +020083config HASWELL_HIDE_PEG_FROM_MRC
84 bool "Hide PEG devices from MRC to work around hardcoded MRC behavior"
85 default y
86 help
87 If set, hides all PEG devices from MRC. This allows the iGPU
88 to be used even when a dedicated graphics card is present.
89 However, it prevents MRC from programming PEG AFE registers,
90 which can make PEG devices unstable. When unsure, choose N.
91
Arthur Heymans77d5e742019-01-03 21:11:45 +010092# The UEFI System Agent binary needs to be at a fixed offset in the flash
93# and can therefore only reside in the COREBOOT fmap region
94config RO_REGION_ONLY
95 string
96 depends on VBOOT
97 default "mrc.bin"
98
Nico Huber612a8672019-02-19 19:11:29 +010099config INTEL_GMA_BCLV_OFFSET
100 default 0x48254
101
Angel Pons1be9f582020-07-03 21:31:17 +0200102config ENABLE_DDR_2X_REFRESH
103 bool "Enable DRAM Refresh 2x support"
104 default n
105 help
106 When enabled, the memory controller will refresh the DRAM twice as often.
107 This probably only happens when the DRAM gets hot, but what MRC exactly
108 does when this setting is enabled has not been investigated.
109
Angel Ponsf95b9b42021-01-20 01:10:48 +0100110config FIXED_MCHBAR_MMIO_BASE
111 default 0xfed10000
112
113config FIXED_DMIBAR_MMIO_BASE
114 default 0xfed18000
115
116config FIXED_EPBAR_MMIO_BASE
117 default 0xfed19000
118
Aaron Durbin76c37002012-10-30 09:03:43 -0500119endif