blob: f68978040f8e328d0a4201f3b0103e17659aac0f [file] [log] [blame]
Aaron Durbin76c37002012-10-30 09:03:43 -05001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2010 Google Inc.
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
15## You should have received a copy of the GNU General Public License
16## along with this program; if not, write to the Free Software
17## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18##
19
20config NORTHBRIDGE_INTEL_HASWELL
21 bool
22 select CACHE_MRC_BIN
23 select CPU_INTEL_HASWELL
24 select REQUIRES_BLOB
Aaron Durbin6d04f0f2012-10-31 22:57:16 -050025 select MMCONF_SUPPORT_DEFAULT
Aaron Durbin76c37002012-10-30 09:03:43 -050026
27if NORTHBRIDGE_INTEL_HASWELL
28
Aaron Durbin6d04f0f2012-10-31 22:57:16 -050029config BOOTBLOCK_NORTHBRIDGE_INIT
30 string
31 default "northbridge/intel/haswell/bootblock.c"
32
Aaron Durbin76c37002012-10-30 09:03:43 -050033config VGA_BIOS_ID
34 string
35 default "8086,0166"
36
37config EXTERNAL_MRC_BLOB
38 bool
39 default n
40
41config CACHE_MRC_SIZE_KB
42 int
43 default 512
44
45# FIXME: build from rom size
46config MRC_CACHE_BASE
47 hex
48 default 0xff800000
49
50config MRC_CACHE_LOCATION
51 hex
52 depends on !CHROMEOS
53 default 0x370000
54
55config MRC_CACHE_SIZE
56 hex
57 depends on !CHROMEOS
58 default 0x10000
59
60config DCACHE_RAM_BASE
61 hex
Aaron Durbin3d0071b2013-01-18 14:32:50 -060062 default 0xff7c0000
Aaron Durbin76c37002012-10-30 09:03:43 -050063
64config DCACHE_RAM_SIZE
65 hex
Aaron Durbin3d0071b2013-01-18 14:32:50 -060066 default 0x10000
67 help
68 The size of the cache-as-ram region required during bootblock
69 and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
70 must add up to a power of 2.
Aaron Durbin76c37002012-10-30 09:03:43 -050071
72config DCACHE_RAM_MRC_VAR_SIZE
73 hex
Aaron Durbin3d0071b2013-01-18 14:32:50 -060074 default 0x30000
75 help
76 The amount of cache-as-ram region required by the reference code.
77
78config DCACHE_RAM_ROMSTAGE_STACK_SIZE
79 hex
80 default 0x2000
81 help
82 The amount of anticipated stack usage from the data cache
83 during pre-ram rom stage execution.
Aaron Durbin76c37002012-10-30 09:03:43 -050084
85config HAVE_MRC
86 bool "Add a System Agent binary"
87 help
88 Select this option to add a System Agent binary to
89 the resulting coreboot image.
90
91 Note: Without this binary coreboot will not work
92
93config MRC_FILE
94 string "Intel System Agent path and filename"
95 depends on HAVE_MRC
96 default "mrc.bin"
97 help
98 The path and filename of the file to use as System Agent
99 binary.
100
101config CBFS_SIZE
102 hex "Size of CBFS filesystem in ROM"
103 default 0x100000
104 help
105 On Haswell systems the firmware image has to store a lot more
106 than just coreboot, including:
107 - a firmware descriptor
108 - Intel Management Engine firmware
109 - MRC cache information
110 This option allows to limit the size of the CBFS portion in the
111 firmware image.
112
113endif