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Elyes HAOUAS36787b02020-05-07 12:07:24 +02001# This file is part of the coreboot project.
2# SPDX-License-Identifier: GPL-2.0-only
Aaron Durbin76c37002012-10-30 09:03:43 -05003
4config NORTHBRIDGE_INTEL_HASWELL
5 bool
Aaron Durbin76c37002012-10-30 09:03:43 -05006 select CPU_INTEL_HASWELL
Arthur Heymansf300f362018-01-27 13:39:12 +01007 select CACHE_MRC_SETTINGS
Furquan Shaikh77f48cd2013-08-19 10:16:50 -07008 select INTEL_DDI
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +01009 select INTEL_GMA_ACPI
Arthur Heymansd893a262018-12-19 16:54:06 +010010 select BOOTBLOCK_CONSOLE
Aaron Durbin76c37002012-10-30 09:03:43 -050011
12if NORTHBRIDGE_INTEL_HASWELL
13
Arthur Heymans77d5e742019-01-03 21:11:45 +010014config HASWELL_VBOOT_IN_BOOTBLOCK
15 depends on VBOOT
16 bool "Start verstage in bootblock"
17 default y
18 select VBOOT_STARTS_IN_BOOTBLOCK
19 select VBOOT_SEPARATE_VERSTAGE
20 help
21 Haswell can either start verstage in a separate stage
22 right after the bootblock has run or it can start it
23 after romstage for compatibility reasons.
Joel Kitching82d73e22019-04-30 13:13:40 +080024 Haswell however uses a mrc.bin to initialize memory which
Arthur Heymans77d5e742019-01-03 21:11:45 +010025 needs to be located at a fixed offset. Therefore even with
26 a separate verstage starting after the bootblock that same
27 binary is used meaning a jump is made from RW to the RO region
28 and back to the RW region after the binary is done.
29
Julius Werner1210b412017-03-27 19:26:32 -070030config VBOOT
Joel Kitching6672bd82019-04-10 16:06:21 +080031 select VBOOT_MUST_REQUEST_DISPLAY
Arthur Heymans77d5e742019-01-03 21:11:45 +010032 select VBOOT_STARTS_IN_ROMSTAGE if !HASWELL_VBOOT_IN_BOOTBLOCK
Julius Werner1210b412017-03-27 19:26:32 -070033
Aaron Durbin76c37002012-10-30 09:03:43 -050034config VGA_BIOS_ID
35 string
36 default "8086,0166"
37
Elyes HAOUASef169d62018-09-14 10:28:52 +020038config MMCONF_BASE_ADDRESS
39 hex
40 default 0xf0000000
41
Aaron Durbin76c37002012-10-30 09:03:43 -050042config DCACHE_RAM_BASE
43 hex
Aaron Durbin3d0071b2013-01-18 14:32:50 -060044 default 0xff7c0000
Aaron Durbin76c37002012-10-30 09:03:43 -050045
46config DCACHE_RAM_SIZE
47 hex
Aaron Durbin3d0071b2013-01-18 14:32:50 -060048 default 0x10000
49 help
50 The size of the cache-as-ram region required during bootblock
51 and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
52 must add up to a power of 2.
Aaron Durbin76c37002012-10-30 09:03:43 -050053
54config DCACHE_RAM_MRC_VAR_SIZE
55 hex
Aaron Durbin3d0071b2013-01-18 14:32:50 -060056 default 0x30000
57 help
58 The amount of cache-as-ram region required by the reference code.
59
Arthur Heymans8e646e72018-06-05 11:19:22 +020060config DCACHE_BSP_STACK_SIZE
61 hex
62 default 0x2000
63 help
64 The amount of anticipated stack usage in CAR by bootblock and
65 other stages.
66
Aaron Durbin76c37002012-10-30 09:03:43 -050067config HAVE_MRC
68 bool "Add a System Agent binary"
69 help
70 Select this option to add a System Agent binary to
71 the resulting coreboot image.
72
73 Note: Without this binary coreboot will not work
74
75config MRC_FILE
76 string "Intel System Agent path and filename"
77 depends on HAVE_MRC
78 default "mrc.bin"
79 help
80 The path and filename of the file to use as System Agent
81 binary.
82
Stefan Reinauerf1aabec2014-01-22 15:16:30 -080083config PRE_GRAPHICS_DELAY
Stefan Reinauer7034b9e2014-02-11 16:18:07 -080084 int "Graphics initialization delay in ms"
Stefan Reinauerf1aabec2014-01-22 15:16:30 -080085 default 0
86 help
87 On some systems, coreboot boots so fast that connected monitors
88 (mostly TVs) won't be able to wake up fast enough to talk to the
89 VBIOS. On those systems we need to wait for a bit before executing
90 the VBIOS.
91
Arthur Heymans77d5e742019-01-03 21:11:45 +010092# The UEFI System Agent binary needs to be at a fixed offset in the flash
93# and can therefore only reside in the COREBOOT fmap region
94config RO_REGION_ONLY
95 string
96 depends on VBOOT
97 default "mrc.bin"
98
Nico Huber612a8672019-02-19 19:11:29 +010099config INTEL_GMA_BCLV_OFFSET
100 default 0x48254
101
Aaron Durbin76c37002012-10-30 09:03:43 -0500102endif