Elyes HAOUAS | 36787b0 | 2020-05-07 12:07:24 +0200 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 2 | |
| 3 | config NORTHBRIDGE_INTEL_HASWELL |
| 4 | bool |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 5 | select CPU_INTEL_HASWELL |
Arthur Heymans | f300f36 | 2018-01-27 13:39:12 +0100 | [diff] [blame] | 6 | select CACHE_MRC_SETTINGS |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 7 | select INTEL_DDI |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 8 | select INTEL_GMA_ACPI |
Arthur Heymans | d893a26 | 2018-12-19 16:54:06 +0100 | [diff] [blame] | 9 | select BOOTBLOCK_CONSOLE |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 10 | |
| 11 | if NORTHBRIDGE_INTEL_HASWELL |
| 12 | |
Arthur Heymans | 77d5e74 | 2019-01-03 21:11:45 +0100 | [diff] [blame] | 13 | config HASWELL_VBOOT_IN_BOOTBLOCK |
| 14 | depends on VBOOT |
| 15 | bool "Start verstage in bootblock" |
| 16 | default y |
| 17 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 18 | select VBOOT_SEPARATE_VERSTAGE |
| 19 | help |
| 20 | Haswell can either start verstage in a separate stage |
| 21 | right after the bootblock has run or it can start it |
| 22 | after romstage for compatibility reasons. |
Joel Kitching | 82d73e2 | 2019-04-30 13:13:40 +0800 | [diff] [blame] | 23 | Haswell however uses a mrc.bin to initialize memory which |
Arthur Heymans | 77d5e74 | 2019-01-03 21:11:45 +0100 | [diff] [blame] | 24 | needs to be located at a fixed offset. Therefore even with |
| 25 | a separate verstage starting after the bootblock that same |
| 26 | binary is used meaning a jump is made from RW to the RO region |
| 27 | and back to the RW region after the binary is done. |
| 28 | |
Julius Werner | 1210b41 | 2017-03-27 19:26:32 -0700 | [diff] [blame] | 29 | config VBOOT |
Joel Kitching | 6672bd8 | 2019-04-10 16:06:21 +0800 | [diff] [blame] | 30 | select VBOOT_MUST_REQUEST_DISPLAY |
Arthur Heymans | 77d5e74 | 2019-01-03 21:11:45 +0100 | [diff] [blame] | 31 | select VBOOT_STARTS_IN_ROMSTAGE if !HASWELL_VBOOT_IN_BOOTBLOCK |
Julius Werner | 1210b41 | 2017-03-27 19:26:32 -0700 | [diff] [blame] | 32 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 33 | config VGA_BIOS_ID |
| 34 | string |
| 35 | default "8086,0166" |
| 36 | |
Elyes HAOUAS | ef169d6 | 2018-09-14 10:28:52 +0200 | [diff] [blame] | 37 | config MMCONF_BASE_ADDRESS |
| 38 | hex |
| 39 | default 0xf0000000 |
| 40 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 41 | config DCACHE_RAM_BASE |
| 42 | hex |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 43 | default 0xff7c0000 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 44 | |
| 45 | config DCACHE_RAM_SIZE |
| 46 | hex |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 47 | default 0x10000 |
| 48 | help |
| 49 | The size of the cache-as-ram region required during bootblock |
| 50 | and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE |
| 51 | must add up to a power of 2. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 52 | |
| 53 | config DCACHE_RAM_MRC_VAR_SIZE |
| 54 | hex |
Aaron Durbin | 3d0071b | 2013-01-18 14:32:50 -0600 | [diff] [blame] | 55 | default 0x30000 |
| 56 | help |
| 57 | The amount of cache-as-ram region required by the reference code. |
| 58 | |
Arthur Heymans | 8e646e7 | 2018-06-05 11:19:22 +0200 | [diff] [blame] | 59 | config DCACHE_BSP_STACK_SIZE |
| 60 | hex |
| 61 | default 0x2000 |
| 62 | help |
| 63 | The amount of anticipated stack usage in CAR by bootblock and |
| 64 | other stages. |
| 65 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 66 | config HAVE_MRC |
| 67 | bool "Add a System Agent binary" |
| 68 | help |
| 69 | Select this option to add a System Agent binary to |
| 70 | the resulting coreboot image. |
| 71 | |
| 72 | Note: Without this binary coreboot will not work |
| 73 | |
| 74 | config MRC_FILE |
| 75 | string "Intel System Agent path and filename" |
| 76 | depends on HAVE_MRC |
| 77 | default "mrc.bin" |
| 78 | help |
| 79 | The path and filename of the file to use as System Agent |
| 80 | binary. |
| 81 | |
Stefan Reinauer | f1aabec | 2014-01-22 15:16:30 -0800 | [diff] [blame] | 82 | config PRE_GRAPHICS_DELAY |
Stefan Reinauer | 7034b9e | 2014-02-11 16:18:07 -0800 | [diff] [blame] | 83 | int "Graphics initialization delay in ms" |
Stefan Reinauer | f1aabec | 2014-01-22 15:16:30 -0800 | [diff] [blame] | 84 | default 0 |
| 85 | help |
| 86 | On some systems, coreboot boots so fast that connected monitors |
| 87 | (mostly TVs) won't be able to wake up fast enough to talk to the |
| 88 | VBIOS. On those systems we need to wait for a bit before executing |
| 89 | the VBIOS. |
| 90 | |
Arthur Heymans | 77d5e74 | 2019-01-03 21:11:45 +0100 | [diff] [blame] | 91 | # The UEFI System Agent binary needs to be at a fixed offset in the flash |
| 92 | # and can therefore only reside in the COREBOOT fmap region |
| 93 | config RO_REGION_ONLY |
| 94 | string |
| 95 | depends on VBOOT |
| 96 | default "mrc.bin" |
| 97 | |
Nico Huber | 612a867 | 2019-02-19 19:11:29 +0100 | [diff] [blame] | 98 | config INTEL_GMA_BCLV_OFFSET |
| 99 | default 0x48254 |
| 100 | |
Angel Pons | 1be9f58 | 2020-07-03 21:31:17 +0200 | [diff] [blame^] | 101 | config ENABLE_DDR_2X_REFRESH |
| 102 | bool "Enable DRAM Refresh 2x support" |
| 103 | default n |
| 104 | help |
| 105 | When enabled, the memory controller will refresh the DRAM twice as often. |
| 106 | This probably only happens when the DRAM gets hot, but what MRC exactly |
| 107 | does when this setting is enabled has not been investigated. |
| 108 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 109 | endif |