blob: 5c8caea92d86abdff77f4e5845d1453e5e6dcb86 [file] [log] [blame]
Aaron Durbin76c37002012-10-30 09:03:43 -05001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2010 Google Inc.
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
Aaron Durbin76c37002012-10-30 09:03:43 -050015
16config NORTHBRIDGE_INTEL_HASWELL
17 bool
Aaron Durbin76c37002012-10-30 09:03:43 -050018 select CPU_INTEL_HASWELL
Arthur Heymansf300f362018-01-27 13:39:12 +010019 select CACHE_MRC_SETTINGS
Furquan Shaikh77f48cd2013-08-19 10:16:50 -070020 select INTEL_DDI
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +010021 select INTEL_GMA_ACPI
Arthur Heymans410f2562017-01-25 15:27:52 +010022 select RELOCATABLE_RAMSTAGE
23 select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
Aaron Durbin76c37002012-10-30 09:03:43 -050024
25if NORTHBRIDGE_INTEL_HASWELL
26
Julius Werner1210b412017-03-27 19:26:32 -070027config VBOOT
28 select VBOOT_STARTS_IN_ROMSTAGE
29
Aaron Durbin6d04f0f2012-10-31 22:57:16 -050030config BOOTBLOCK_NORTHBRIDGE_INIT
31 string
32 default "northbridge/intel/haswell/bootblock.c"
33
Aaron Durbin76c37002012-10-30 09:03:43 -050034config VGA_BIOS_ID
35 string
36 default "8086,0166"
37
Aaron Durbin76c37002012-10-30 09:03:43 -050038config CACHE_MRC_SIZE_KB
39 int
40 default 512
41
Aaron Durbin76c37002012-10-30 09:03:43 -050042config DCACHE_RAM_BASE
43 hex
Aaron Durbin3d0071b2013-01-18 14:32:50 -060044 default 0xff7c0000
Aaron Durbin76c37002012-10-30 09:03:43 -050045
46config DCACHE_RAM_SIZE
47 hex
Aaron Durbin3d0071b2013-01-18 14:32:50 -060048 default 0x10000
49 help
50 The size of the cache-as-ram region required during bootblock
51 and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
52 must add up to a power of 2.
Aaron Durbin76c37002012-10-30 09:03:43 -050053
54config DCACHE_RAM_MRC_VAR_SIZE
55 hex
Aaron Durbin3d0071b2013-01-18 14:32:50 -060056 default 0x30000
57 help
58 The amount of cache-as-ram region required by the reference code.
59
60config DCACHE_RAM_ROMSTAGE_STACK_SIZE
61 hex
62 default 0x2000
63 help
64 The amount of anticipated stack usage from the data cache
Elyes HAOUAS15279a92016-07-28 21:05:26 +020065 during pre-ram ROM stage execution.
Aaron Durbin76c37002012-10-30 09:03:43 -050066
Aaron Durbin76c37002012-10-30 09:03:43 -050067config HAVE_MRC
68 bool "Add a System Agent binary"
69 help
70 Select this option to add a System Agent binary to
71 the resulting coreboot image.
72
73 Note: Without this binary coreboot will not work
74
75config MRC_FILE
76 string "Intel System Agent path and filename"
77 depends on HAVE_MRC
78 default "mrc.bin"
79 help
80 The path and filename of the file to use as System Agent
81 binary.
82
Stefan Reinauerf1aabec2014-01-22 15:16:30 -080083config PRE_GRAPHICS_DELAY
Stefan Reinauer7034b9e2014-02-11 16:18:07 -080084 int "Graphics initialization delay in ms"
Stefan Reinauerf1aabec2014-01-22 15:16:30 -080085 default 0
86 help
87 On some systems, coreboot boots so fast that connected monitors
88 (mostly TVs) won't be able to wake up fast enough to talk to the
89 VBIOS. On those systems we need to wait for a bit before executing
90 the VBIOS.
91
Aaron Durbin76c37002012-10-30 09:03:43 -050092endif