blob: e51ac3cf09bac6b7c3d53782a4f0fe1d5d98b6ae [file] [log] [blame]
Aaron Durbin76c37002012-10-30 09:03:43 -05001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2010 Google Inc.
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
15## You should have received a copy of the GNU General Public License
16## along with this program; if not, write to the Free Software
Patrick Georgib890a122015-03-26 15:17:45 +010017## Foundation, Inc.
Aaron Durbin76c37002012-10-30 09:03:43 -050018##
19
20config NORTHBRIDGE_INTEL_HASWELL
21 bool
22 select CACHE_MRC_BIN
23 select CPU_INTEL_HASWELL
24 select REQUIRES_BLOB
Kyösti Mälkki15c4ab72013-07-02 11:37:35 +030025 select MMCONF_SUPPORT
Aaron Durbin6d04f0f2012-10-31 22:57:16 -050026 select MMCONF_SUPPORT_DEFAULT
Furquan Shaikh77f48cd2013-08-19 10:16:50 -070027 select INTEL_DDI
28 select INTEL_DP
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +010029 select INTEL_GMA_ACPI
Aaron Durbin76c37002012-10-30 09:03:43 -050030
31if NORTHBRIDGE_INTEL_HASWELL
32
Aaron Durbin6d04f0f2012-10-31 22:57:16 -050033config BOOTBLOCK_NORTHBRIDGE_INIT
34 string
35 default "northbridge/intel/haswell/bootblock.c"
36
Aaron Durbin76c37002012-10-30 09:03:43 -050037config VGA_BIOS_ID
38 string
39 default "8086,0166"
40
Aaron Durbin76c37002012-10-30 09:03:43 -050041config CACHE_MRC_SIZE_KB
42 int
43 default 512
44
Aaron Durbin76c37002012-10-30 09:03:43 -050045config MRC_CACHE_SIZE
46 hex
47 depends on !CHROMEOS
48 default 0x10000
49
50config DCACHE_RAM_BASE
51 hex
Aaron Durbin3d0071b2013-01-18 14:32:50 -060052 default 0xff7c0000
Aaron Durbin76c37002012-10-30 09:03:43 -050053
54config DCACHE_RAM_SIZE
55 hex
Aaron Durbin3d0071b2013-01-18 14:32:50 -060056 default 0x10000
57 help
58 The size of the cache-as-ram region required during bootblock
59 and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
60 must add up to a power of 2.
Aaron Durbin76c37002012-10-30 09:03:43 -050061
62config DCACHE_RAM_MRC_VAR_SIZE
63 hex
Aaron Durbin3d0071b2013-01-18 14:32:50 -060064 default 0x30000
65 help
66 The amount of cache-as-ram region required by the reference code.
67
68config DCACHE_RAM_ROMSTAGE_STACK_SIZE
69 hex
70 default 0x2000
71 help
72 The amount of anticipated stack usage from the data cache
73 during pre-ram rom stage execution.
Aaron Durbin76c37002012-10-30 09:03:43 -050074
Aaron Durbin76c37002012-10-30 09:03:43 -050075config HAVE_MRC
76 bool "Add a System Agent binary"
77 help
78 Select this option to add a System Agent binary to
79 the resulting coreboot image.
80
81 Note: Without this binary coreboot will not work
82
83config MRC_FILE
84 string "Intel System Agent path and filename"
85 depends on HAVE_MRC
86 default "mrc.bin"
87 help
88 The path and filename of the file to use as System Agent
89 binary.
90
91config CBFS_SIZE
92 hex "Size of CBFS filesystem in ROM"
93 default 0x100000
94 help
95 On Haswell systems the firmware image has to store a lot more
96 than just coreboot, including:
97 - a firmware descriptor
98 - Intel Management Engine firmware
99 - MRC cache information
100 This option allows to limit the size of the CBFS portion in the
101 firmware image.
102
Stefan Reinauerf1aabec2014-01-22 15:16:30 -0800103config PRE_GRAPHICS_DELAY
Stefan Reinauer7034b9e2014-02-11 16:18:07 -0800104 int "Graphics initialization delay in ms"
Stefan Reinauerf1aabec2014-01-22 15:16:30 -0800105 default 0
106 help
107 On some systems, coreboot boots so fast that connected monitors
108 (mostly TVs) won't be able to wake up fast enough to talk to the
109 VBIOS. On those systems we need to wait for a bit before executing
110 the VBIOS.
111
Aaron Durbin76c37002012-10-30 09:03:43 -0500112endif