Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 1 | config SOC_INTEL_SKYLAKE |
| 2 | bool |
| 3 | help |
| 4 | Intel Skylake support |
| 5 | |
Rizwan Qureshi | 0700dca | 2017-02-09 15:57:45 +0530 | [diff] [blame] | 6 | config SOC_INTEL_KABYLAKE |
| 7 | bool |
| 8 | default n |
| 9 | select SOC_INTEL_SKYLAKE |
| 10 | help |
| 11 | Intel Kabylake support |
| 12 | |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 13 | if SOC_INTEL_SKYLAKE |
| 14 | |
| 15 | config CPU_SPECIFIC_OPTIONS |
| 16 | def_bool y |
Aaron Durbin | e0a4914 | 2016-07-13 23:20:51 -0500 | [diff] [blame] | 17 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Vadim Bendebury | 5542bb6 | 2018-02-05 19:59:09 -0800 | [diff] [blame] | 18 | select ACPI_NHLT |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 19 | select ARCH_BOOTBLOCK_X86_32 |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 20 | select ARCH_RAMSTAGE_X86_32 |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 21 | select ARCH_ROMSTAGE_X86_32 |
| 22 | select ARCH_VERSTAGE_X86_32 |
Teo Boon Tiong | 673a4d0 | 2016-11-10 21:06:51 +0800 | [diff] [blame] | 23 | select BOOTBLOCK_CONSOLE |
Aaron Durbin | e4cc8cd | 2016-08-11 23:55:39 -0500 | [diff] [blame] | 24 | select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH |
Aaron Durbin | e8e118d | 2016-08-12 15:00:10 -0500 | [diff] [blame] | 25 | select BOOT_DEVICE_SUPPORTS_WRITES |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 26 | select CACHE_MRC_SETTINGS |
Kyösti Mälkki | 730df3c | 2016-06-18 07:39:31 +0300 | [diff] [blame] | 27 | select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 28 | select COLLECT_TIMESTAMPS |
Duncan Laurie | 135c2c4 | 2016-10-17 19:47:51 -0700 | [diff] [blame] | 29 | select COMMON_FADT |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 30 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Vadim Bendebury | 5542bb6 | 2018-02-05 19:59:09 -0800 | [diff] [blame] | 31 | select C_ENVIRONMENT_BOOTBLOCK |
Aaron Durbin | ffdf901 | 2015-07-24 13:00:36 -0500 | [diff] [blame] | 32 | select GENERIC_GPIO_LIB |
Vadim Bendebury | 5542bb6 | 2018-02-05 19:59:09 -0800 | [diff] [blame] | 33 | select HAVE_FSP_GOP |
Stefan Tauner | ef8b957 | 2018-09-06 00:34:28 +0200 | [diff] [blame] | 34 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 35 | select HAVE_MONOTONIC_TIMER |
| 36 | select HAVE_SMI_HANDLER |
Patrick Rudolph | c7edf18 | 2017-09-26 19:34:35 +0200 | [diff] [blame] | 37 | select INTEL_GMA_ACPI |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 38 | select IOAPIC |
Duncan Laurie | 205ed2d | 2016-06-02 15:23:42 -0700 | [diff] [blame] | 39 | select MRC_SETTINGS_PROTECT |
Vadim Bendebury | 5542bb6 | 2018-02-05 19:59:09 -0800 | [diff] [blame] | 40 | select NO_FIXED_XIP_ROM_SIZE |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 41 | select PARALLEL_MP |
Furquan Shaikh | a585358 | 2017-05-06 12:40:15 -0700 | [diff] [blame] | 42 | select PARALLEL_MP_AP_WORK |
Subrata Banik | 93ebe49 | 2017-03-14 18:24:47 +0530 | [diff] [blame] | 43 | select PCIEX_LENGTH_64MB |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 44 | select REG_SCRIPT |
Aaron Durbin | 16246ea | 2016-08-05 21:23:37 -0500 | [diff] [blame] | 45 | select RTC |
Subrata Banik | 46a7178 | 2017-06-02 18:52:24 +0530 | [diff] [blame] | 46 | select SA_ENABLE_DPR |
Vadim Bendebury | 5542bb6 | 2018-02-05 19:59:09 -0800 | [diff] [blame] | 47 | select SMM_TSEG |
| 48 | select SMP |
Julien Viard de Galbert | 2912e8e | 2018-08-14 16:15:26 +0200 | [diff] [blame] | 49 | select PMC_GLOBAL_RESET_ENABLE_LOCK |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 50 | select SOC_INTEL_COMMON |
Duncan Laurie | a1c8b34d | 2015-09-08 16:12:44 -0700 | [diff] [blame] | 51 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
Subrata Banik | e074d62 | 2017-02-16 16:16:37 +0530 | [diff] [blame] | 52 | select SOC_INTEL_COMMON_BLOCK |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 53 | select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG |
Barnali Sarkar | 0a203d1 | 2017-05-04 18:02:17 +0530 | [diff] [blame] | 54 | select SOC_INTEL_COMMON_BLOCK_CPU |
Barnali Sarkar | 7327386 | 2017-06-13 20:22:33 +0530 | [diff] [blame] | 55 | select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
Furquan Shaikh | 2c36889 | 2018-10-18 16:22:37 -0700 | [diff] [blame] | 56 | select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT |
Hannah Williams | 1760cd3 | 2017-04-06 20:54:11 -0700 | [diff] [blame] | 57 | select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS |
Vadim Bendebury | 5542bb6 | 2018-02-05 19:59:09 -0800 | [diff] [blame] | 58 | select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL |
Furquan Shaikh | 05a6f29 | 2017-03-31 14:02:47 -0700 | [diff] [blame] | 59 | select SOC_INTEL_COMMON_BLOCK_GSPI |
Furquan Shaikh | 31bff01 | 2018-09-29 23:31:04 -0700 | [diff] [blame] | 60 | select SOC_INTEL_COMMON_BLOCK_HDA |
Subrata Banik | 93ebe49 | 2017-03-14 18:24:47 +0530 | [diff] [blame] | 61 | select SOC_INTEL_COMMON_BLOCK_SA |
Pratik Prajapati | a04aa3d | 2017-06-12 23:02:36 -0700 | [diff] [blame] | 62 | select SOC_INTEL_COMMON_BLOCK_SGX |
Subrata Banik | ece173c | 2017-12-14 18:18:34 +0530 | [diff] [blame] | 63 | select SOC_INTEL_COMMON_BLOCK_SMM |
| 64 | select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 65 | select SOC_INTEL_COMMON_BLOCK_UART |
Matt DeVillier | 969ef10 | 2018-03-21 20:47:52 -0500 | [diff] [blame] | 66 | select SOC_INTEL_COMMON_BLOCK_VMX |
Subrata Banik | f513ceb | 2018-05-17 15:57:43 +0530 | [diff] [blame] | 67 | select SOC_INTEL_COMMON_PCH_BASE |
Aaron Durbin | c14a1a9 | 2016-06-28 15:41:07 -0500 | [diff] [blame] | 68 | select SOC_INTEL_COMMON_NHLT |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 69 | select SOC_INTEL_COMMON_RESET |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 70 | select SSE2 |
| 71 | select SUPPORT_CPU_UCODE_IN_CBFS |
| 72 | select TSC_CONSTANT_RATE |
Aamir Bohra | 842776e | 2017-05-25 14:12:01 +0530 | [diff] [blame] | 73 | select TSC_MONOTONIC_TIMER |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 74 | select TSC_SYNC_MFENCE |
| 75 | select UDELAY_TSC |
Praveen hodagatta pranesh | ccd1746 | 2018-11-03 01:49:15 +0800 | [diff] [blame] | 76 | select FSP_T_XIP if FSP_CAR |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 77 | |
Arthur Heymans | 27d3f71 | 2018-01-05 17:51:46 +0100 | [diff] [blame] | 78 | config CPU_INTEL_NUM_FIT_ENTRIES |
| 79 | int |
| 80 | default 10 |
| 81 | |
Naresh G Solanki | fe517f6 | 2016-10-17 17:21:08 +0530 | [diff] [blame] | 82 | config MAINBOARD_USES_FSP2_0 |
| 83 | bool |
| 84 | default n |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 85 | |
| 86 | config USE_FSP2_0_DRIVER |
Nico Huber | 956cfa3 | 2017-06-28 12:20:48 +0200 | [diff] [blame] | 87 | def_bool y |
Naresh G Solanki | fe517f6 | 2016-10-17 17:21:08 +0530 | [diff] [blame] | 88 | depends on MAINBOARD_USES_FSP2_0 |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 89 | select PLATFORM_USES_FSP2_0 |
Subrata Banik | 7455881 | 2018-01-25 11:41:04 +0530 | [diff] [blame] | 90 | select UDK_2015_BINDING |
Nico Huber | 29cc331 | 2018-06-06 17:40:02 +0200 | [diff] [blame] | 91 | select INTEL_GMA_ADD_VBT if RUN_FSP_GOP |
Aaron Durbin | 79f0741 | 2017-04-16 21:49:29 -0500 | [diff] [blame] | 92 | select POSTCAR_CONSOLE |
| 93 | select POSTCAR_STAGE |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 94 | |
| 95 | config USE_FSP1_1_DRIVER |
Nico Huber | 956cfa3 | 2017-06-28 12:20:48 +0200 | [diff] [blame] | 96 | def_bool y |
Naresh G Solanki | fe517f6 | 2016-10-17 17:21:08 +0530 | [diff] [blame] | 97 | depends on !MAINBOARD_USES_FSP2_0 |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 98 | select PLATFORM_USES_FSP1_1 |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 99 | select DISPLAY_FSP_ENTRY_POINTS |
| 100 | |
Furquan Shaikh | 610a33a | 2016-07-22 16:17:53 -0700 | [diff] [blame] | 101 | config CHROMEOS |
| 102 | select CHROMEOS_RAMOOPS_DYNAMIC |
Julius Werner | 58c3938 | 2017-02-13 17:53:29 -0800 | [diff] [blame] | 103 | |
| 104 | config VBOOT |
| 105 | select VBOOT_EC_SLOW_UPDATE if VBOOT_EC_SOFTWARE_SYNC |
| 106 | select VBOOT_SEPARATE_VERSTAGE |
Furquan Shaikh | 610a33a | 2016-07-22 16:17:53 -0700 | [diff] [blame] | 107 | select VBOOT_OPROM_MATTERS |
Furquan Shaikh | b8257df | 2016-07-22 09:20:56 -0700 | [diff] [blame] | 108 | select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT |
Aaron Durbin | a6914d2 | 2016-08-24 08:49:29 -0500 | [diff] [blame] | 109 | select VBOOT_STARTS_IN_BOOTBLOCK |
Furquan Shaikh | 2a12e2e | 2016-07-25 11:48:03 -0700 | [diff] [blame] | 110 | select VBOOT_VBNV_CMOS |
| 111 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
Furquan Shaikh | 610a33a | 2016-07-22 16:17:53 -0700 | [diff] [blame] | 112 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 113 | config BOOTBLOCK_RESETS |
| 114 | string |
| 115 | default "soc/intel/common/reset.c" |
| 116 | |
Martin Roth | 59ff340 | 2016-02-09 09:06:46 -0700 | [diff] [blame] | 117 | config CBFS_SIZE |
| 118 | hex |
| 119 | default 0x200000 |
| 120 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 121 | config CPU_ADDR_BITS |
| 122 | int |
| 123 | default 36 |
| 124 | |
| 125 | config DCACHE_RAM_BASE |
Arthur Heymans | 432ac61 | 2017-06-13 14:17:05 +0200 | [diff] [blame] | 126 | hex |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 127 | default 0xfef00000 |
| 128 | |
| 129 | config DCACHE_RAM_SIZE |
Arthur Heymans | 432ac61 | 2017-06-13 14:17:05 +0200 | [diff] [blame] | 130 | hex |
Rizwan Qureshi | 3ad6356 | 2016-08-14 15:48:33 +0530 | [diff] [blame] | 131 | default 0x40000 |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 132 | help |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 133 | The size of the cache-as-ram region required during bootblock |
| 134 | and/or romstage. |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 135 | |
Subrata Banik | 68d5d8b | 2016-07-18 14:13:52 +0530 | [diff] [blame] | 136 | config DCACHE_BSP_STACK_SIZE |
| 137 | hex |
| 138 | default 0x4000 |
| 139 | help |
| 140 | The amount of anticipated stack usage in CAR by bootblock and |
| 141 | other stages. |
| 142 | |
| 143 | config C_ENV_BOOTBLOCK_SIZE |
| 144 | hex |
Furquan Shaikh | 7038596 | 2016-08-24 10:28:30 -0700 | [diff] [blame] | 145 | default 0xC000 |
Subrata Banik | 68d5d8b | 2016-07-18 14:13:52 +0530 | [diff] [blame] | 146 | |
Subrata Banik | 086730b | 2015-12-02 11:42:04 +0530 | [diff] [blame] | 147 | config EXCLUDE_NATIVE_SD_INTERFACE |
| 148 | bool |
| 149 | default n |
| 150 | help |
| 151 | If you set this option to n, will not use native SD controller. |
| 152 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 153 | config HEAP_SIZE |
| 154 | hex |
| 155 | default 0x80000 |
| 156 | |
| 157 | config IED_REGION_SIZE |
| 158 | hex |
| 159 | default 0x400000 |
| 160 | |
Subrata Banik | e7ceae7 | 2017-03-08 17:59:40 +0530 | [diff] [blame] | 161 | config PCR_BASE_ADDRESS |
| 162 | hex |
| 163 | default 0xfd000000 |
| 164 | help |
| 165 | This option allows you to select MMIO Base Address of sideband bus. |
| 166 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 167 | config SERIRQ_CONTINUOUS_MODE |
| 168 | bool |
pchandri | 1d77c72 | 2015-09-09 17:22:09 -0700 | [diff] [blame] | 169 | default n |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 170 | help |
| 171 | If you set this option to y, the serial IRQ machine will be |
| 172 | operated in continuous mode. |
| 173 | |
| 174 | config SMM_RESERVED_SIZE |
| 175 | hex |
| 176 | default 0x200000 |
| 177 | |
| 178 | config SMM_TSEG_SIZE |
| 179 | hex |
| 180 | default 0x800000 |
| 181 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 182 | config VGA_BIOS_ID |
| 183 | string |
| 184 | default "8086,0406" |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 185 | |
Aaron Durbin | e33a172 | 2015-07-30 16:52:56 -0500 | [diff] [blame] | 186 | config UART_DEBUG |
| 187 | bool "Enable UART debug port." |
Aaron Durbin | e33a172 | 2015-07-30 16:52:56 -0500 | [diff] [blame] | 188 | default n |
Martin Roth | 1afcb23 | 2015-08-15 17:36:15 -0600 | [diff] [blame] | 189 | select CONSOLE_SERIAL |
Aaron Durbin | e33a172 | 2015-07-30 16:52:56 -0500 | [diff] [blame] | 190 | select DRIVERS_UART |
Aaron Durbin | e33a172 | 2015-07-30 16:52:56 -0500 | [diff] [blame] | 191 | select DRIVERS_UART_8250MEM_32 |
Furquan Shaikh | b168db7 | 2016-08-01 19:37:38 -0700 | [diff] [blame] | 192 | select NO_UART_ON_SUPERIO |
Aaron Durbin | e33a172 | 2015-07-30 16:52:56 -0500 | [diff] [blame] | 193 | |
Subrata Banik | 19a7ade | 2017-08-14 11:55:10 +0530 | [diff] [blame] | 194 | config UART_FOR_CONSOLE |
| 195 | int "Index for LPSS UART port to use for console" |
| 196 | default 2 if DRIVERS_UART_8250MEM |
Subrata Banik | b045d4c | 2017-08-30 11:47:32 +0530 | [diff] [blame] | 197 | default 0 |
Subrata Banik | 19a7ade | 2017-08-14 11:55:10 +0530 | [diff] [blame] | 198 | help |
| 199 | Index for LPSS UART port to use for console: |
| 200 | 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2 |
| 201 | |
Teo Boon Tiong | 2fc06c8 | 2016-09-15 11:11:45 +0800 | [diff] [blame] | 202 | config SKYLAKE_SOC_PCH_H |
| 203 | bool |
| 204 | default n |
| 205 | help |
| 206 | Choose this option if you have a PCH-H chipset. |
| 207 | |
Aaron Durbin | 3953e39 | 2015-09-03 00:41:29 -0500 | [diff] [blame] | 208 | config CHIPSET_BOOTBLOCK_INCLUDE |
| 209 | string |
| 210 | default "soc/intel/skylake/bootblock/timestamp.inc" |
| 211 | |
Aaron Durbin | ed8a723 | 2015-11-24 12:35:06 -0600 | [diff] [blame] | 212 | config NHLT_DMIC_2CH |
| 213 | bool |
| 214 | default n |
| 215 | help |
| 216 | Include DSP firmware settings for 2 channel DMIC array. |
| 217 | |
| 218 | config NHLT_DMIC_4CH |
| 219 | bool |
| 220 | default n |
| 221 | help |
| 222 | Include DSP firmware settings for 4 channel DMIC array. |
| 223 | |
| 224 | config NHLT_NAU88L25 |
| 225 | bool |
| 226 | default n |
| 227 | help |
| 228 | Include DSP firmware settings for nau88l25 headset codec. |
| 229 | |
| 230 | config NHLT_MAX98357 |
| 231 | bool |
| 232 | default n |
| 233 | help |
| 234 | Include DSP firmware settings for max98357 amplifier. |
| 235 | |
Duncan Laurie | e6c8a38 | 2018-03-26 02:45:02 -0700 | [diff] [blame] | 236 | config NHLT_MAX98373 |
| 237 | bool |
| 238 | default n |
| 239 | help |
| 240 | Include DSP firmware settings for max98373 amplifier. |
| 241 | |
Aaron Durbin | ed8a723 | 2015-11-24 12:35:06 -0600 | [diff] [blame] | 242 | config NHLT_SSM4567 |
| 243 | bool |
| 244 | default n |
| 245 | help |
| 246 | Include DSP firmware settings for ssm4567 smart amplifier. |
| 247 | |
Duncan Laurie | 4a75a66 | 2017-03-02 10:13:51 -0800 | [diff] [blame] | 248 | config NHLT_RT5514 |
| 249 | bool |
| 250 | default n |
| 251 | help |
| 252 | Include DSP firmware settings for rt5514 DSP. |
| 253 | |
Rizwan Qureshi | 17335fa | 2017-01-14 06:08:21 +0530 | [diff] [blame] | 254 | config NHLT_RT5663 |
| 255 | bool |
| 256 | default n |
| 257 | help |
| 258 | Include DSP firmware settings for rt5663 headset codec. |
| 259 | |
| 260 | config NHLT_MAX98927 |
| 261 | bool |
| 262 | default n |
| 263 | help |
| 264 | Include DSP firmware settings for max98927 amplifier. |
| 265 | |
Naveen Manohar | 83670c5 | 2017-11-04 02:55:09 +0530 | [diff] [blame] | 266 | config NHLT_DA7219 |
| 267 | bool |
| 268 | default n |
| 269 | help |
| 270 | Include DSP firmware settings for DA7219 headset codec. |
| 271 | |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 272 | choice |
| 273 | prompt "Cache-as-ram implementation" |
Subrata Banik | 9e3ba21 | 2018-01-08 15:28:26 +0530 | [diff] [blame] | 274 | default USE_SKYLAKE_CAR_NEM_ENHANCED |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 275 | help |
| 276 | This option allows you to select how cache-as-ram (CAR) is set up. |
| 277 | |
Subrata Banik | 9e3ba21 | 2018-01-08 15:28:26 +0530 | [diff] [blame] | 278 | config USE_SKYLAKE_CAR_NEM_ENHANCED |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 279 | bool "Enhanced Non-evict mode" |
| 280 | select SOC_INTEL_COMMON_BLOCK_CAR |
| 281 | select INTEL_CAR_NEM_ENHANCED |
| 282 | help |
Subrata Banik | 9e3ba21 | 2018-01-08 15:28:26 +0530 | [diff] [blame] | 283 | A current limitation of NEM (Non-Evict mode) is that code and data |
| 284 | sizes are derived from the requirement to not write out any modified |
| 285 | cache line. With NEM, if there is no physical memory behind the |
| 286 | cached area, the modified data will be lost and NEM results will be |
| 287 | inconsistent. ENHANCED NEM guarantees that modified data is always |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 288 | kept in cache while clean data is replaced. |
| 289 | |
| 290 | config USE_SKYLAKE_FSP_CAR |
| 291 | bool "Use FSP CAR" |
| 292 | select FSP_CAR |
| 293 | help |
Subrata Banik | 9e3ba21 | 2018-01-08 15:28:26 +0530 | [diff] [blame] | 294 | Use FSP APIs to initialize and tear down the Cache-As-Ram. |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 295 | |
| 296 | endchoice |
| 297 | |
Patrick Georgi | 6539e10 | 2018-09-13 11:48:43 -0400 | [diff] [blame] | 298 | config FSP_HEADER_PATH |
Patrick Georgi | c6382cd | 2018-10-26 22:03:17 +0200 | [diff] [blame] | 299 | string "Location of FSP headers" |
Patrick Georgi | 6539e10 | 2018-09-13 11:48:43 -0400 | [diff] [blame] | 300 | depends on MAINBOARD_USES_FSP2_0 |
| 301 | # Use KabylakeFsp for both Skylake and Kabylake as it supports both. |
| 302 | # SkylakeFsp is FSP 1.1 and therefore incompatible. |
| 303 | default "3rdparty/fsp/KabylakeFspBinPkg/Include/" if SOC_INTEL_SKYLAKE |
| 304 | default "3rdparty/fsp/KabylakeFspBinPkg/Include/" if SOC_INTEL_KABYLAKE |
| 305 | |
| 306 | config FSP_FD_PATH |
| 307 | string |
| 308 | depends on FSP_USE_REPO |
| 309 | default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" if SOC_INTEL_SKYLAKE |
| 310 | default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" if SOC_INTEL_KABYLAKE |
| 311 | |
Subrata Banik | fbdc719 | 2016-01-19 19:19:15 +0530 | [diff] [blame] | 312 | config SKIP_FSP_CAR |
Martin Roth | b00ddec | 2016-01-31 10:39:47 -0700 | [diff] [blame] | 313 | bool "Skip cache as RAM setup in FSP" |
| 314 | default y |
| 315 | help |
| 316 | Skip Cache as RAM setup in FSP. |
Subrata Banik | fbdc719 | 2016-01-19 19:19:15 +0530 | [diff] [blame] | 317 | |
Aaron Durbin | e56191e | 2016-08-11 09:50:49 -0500 | [diff] [blame] | 318 | config SPI_FLASH_INCLUDE_ALL_DRIVERS |
| 319 | bool |
| 320 | default n |
| 321 | |
Rizwan Qureshi | d8bb69a | 2016-11-08 21:01:09 +0530 | [diff] [blame] | 322 | config MAX_ROOT_PORTS |
| 323 | int |
| 324 | default 24 if PLATFORM_USES_FSP2_0 |
| 325 | default 20 if PLATFORM_USES_FSP1_1 |
| 326 | |
Jenny TC | 2864f85 | 2017-02-09 16:01:59 +0530 | [diff] [blame] | 327 | config NO_FADT_8042 |
| 328 | bool |
| 329 | default n |
| 330 | help |
| 331 | Choose this option if you want to disable 8042 Keyboard |
| 332 | |
Aaron Durbin | 551e4be | 2018-04-10 09:24:54 -0600 | [diff] [blame] | 333 | config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
Furquan Shaikh | 340908a | 2017-04-04 11:47:19 -0700 | [diff] [blame] | 334 | int |
| 335 | default 120 |
| 336 | |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 337 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 338 | int |
Aaron Durbin | 551e4be | 2018-04-10 09:24:54 -0600 | [diff] [blame] | 339 | default SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 340 | |
Furquan Shaikh | 05a6f29 | 2017-03-31 14:02:47 -0700 | [diff] [blame] | 341 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| 342 | int |
| 343 | default 2 |
| 344 | |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 345 | config SOC_INTEL_I2C_DEV_MAX |
| 346 | int |
| 347 | default 6 |
| 348 | |
Aamir Bohra | 1041d39 | 2017-06-02 11:56:14 +0530 | [diff] [blame] | 349 | config CPU_BCLK_MHZ |
| 350 | int |
| 351 | default 100 |
| 352 | |
Furquan Shaikh | 3406dd6 | 2017-08-04 15:58:26 -0700 | [diff] [blame] | 353 | # Clock divider parameters for 115200 baud rate |
| 354 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |
| 355 | hex |
| 356 | default 0x30 |
| 357 | |
| 358 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL |
| 359 | hex |
| 360 | default 0xc35 |
| 361 | |
Furquan Shaikh | a3ad990 | 2018-03-21 10:45:08 -0700 | [diff] [blame] | 362 | config IFD_CHIPSET |
| 363 | string |
| 364 | default "sklkbl" |
| 365 | |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 366 | endif |