Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
Matt DeVillier | 8f42472 | 2019-11-27 22:55:43 -0600 | [diff] [blame] | 3 | # IGD Displays |
| 4 | register "gfx" = "GMA_STATIC_DISPLAYS(0)" |
| 5 | |
Matt DeVillier | f5d15967 | 2019-11-30 16:29:58 -0600 | [diff] [blame] | 6 | register "panel_cfg" = "{ |
| 7 | .up_delay_ms = 100, |
| 8 | .down_delay_ms = 500, |
| 9 | .cycle_delay_ms = 500, |
| 10 | .backlight_on_delay_ms = 1, |
| 11 | .backlight_off_delay_ms = 200, |
| 12 | .backlight_pwm_hz = 1000, |
| 13 | }" |
| 14 | |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 15 | # Deep Sx states |
| 16 | register "deep_s3_enable_ac" = "0" |
Furquan Shaikh | d37107e | 2017-11-08 11:28:10 -0800 | [diff] [blame] | 17 | register "deep_s3_enable_dc" = "0" |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 18 | register "deep_s5_enable_ac" = "1" |
| 19 | register "deep_s5_enable_dc" = "1" |
Furquan Shaikh | 9d867af | 2017-12-03 21:45:47 -0800 | [diff] [blame] | 20 | register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 21 | |
| 22 | # GPE configuration |
| 23 | # Note that GPE events called out in ASL code rely on this |
| 24 | # route. i.e. If this route changes then the affected GPE |
| 25 | # offset bits also need to be changed. |
| 26 | register "gpe0_dw0" = "GPP_B" |
| 27 | register "gpe0_dw1" = "GPP_D" |
| 28 | register "gpe0_dw2" = "GPP_E" |
| 29 | |
| 30 | # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f |
| 31 | register "gen1_dec" = "0x00fc0801" |
| 32 | register "gen2_dec" = "0x000c0201" |
| 33 | # EC memory map range is 0x900-0x9ff |
| 34 | register "gen3_dec" = "0x00fc0901" |
| 35 | |
| 36 | # Enable DPTF |
| 37 | register "dptf_enable" = "1" |
| 38 | |
Rajat Jain | 2671afc | 2017-07-20 19:31:01 -0700 | [diff] [blame] | 39 | # Enable S0ix |
Felix Singer | 743242b | 2023-06-16 01:33:25 +0200 | [diff] [blame] | 40 | register "s0ix_enable" = true |
Rajat Jain | 2671afc | 2017-07-20 19:31:01 -0700 | [diff] [blame] | 41 | |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 42 | # FSP Configuration |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 43 | register "SataSalpSupport" = "0" |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 44 | register "SataPortsEnable[0]" = "0" |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 45 | register "DspEnable" = "1" |
| 46 | register "IoBufferOwnership" = "3" |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 47 | register "SsicPortEnable" = "0" |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 48 | register "ScsEmmcHs400Enabled" = "1" |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 49 | register "SkipExtGfxScan" = "1" |
Angel Pons | 6fadde0 | 2021-04-04 16:11:53 +0200 | [diff] [blame] | 50 | register "SaGv" = "SaGv_Enabled" |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 51 | register "PmConfigSlpS3MinAssert" = "2" # 50ms |
| 52 | register "PmConfigSlpS4MinAssert" = "1" # 1s |
| 53 | register "PmConfigSlpSusMinAssert" = "1" # 500ms |
| 54 | register "PmConfigSlpAMinAssert" = "3" # 2s |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 55 | |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 56 | # VR Settings Configuration for 4 Domains |
| 57 | #+----------------+-------+-------+-------+-------+ |
| 58 | #| Domain/Setting | SA | IA | GTUS | GTS | |
| 59 | #+----------------+-------+-------+-------+-------+ |
| 60 | #| Psi1Threshold | 20A | 20A | 20A | 20A | |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 61 | #| Psi2Threshold | 2A | 2A | 2A | 2A | |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 62 | #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| 63 | #| Psi3Enable | 1 | 1 | 1 | 1 | |
| 64 | #| Psi4Enable | 1 | 1 | 1 | 1 | |
| 65 | #| ImonSlope | 0 | 0 | 0 | 0 | |
| 66 | #| ImonOffset | 0 | 0 | 0 | 0 | |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 67 | #| IccMax | 5A | 24A | 24A | 24A | |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 68 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 69 | #| AcLoadline | 15 | 5.7 | 5.5 | 5.5 | |
| 70 | #| DcLoadline | 14.3 | 4.83 | 4.2 | 4.2 | |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 71 | #+----------------+-------+-------+-------+-------+ |
| 72 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| 73 | .vr_config_enable = 1, |
| 74 | .psi1threshold = VR_CFG_AMP(20), |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 75 | .psi2threshold = VR_CFG_AMP(2), |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 76 | .psi3threshold = VR_CFG_AMP(1), |
| 77 | .psi3enable = 1, |
| 78 | .psi4enable = 1, |
| 79 | .imon_slope = 0x0, |
| 80 | .imon_offset = 0x0, |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 81 | .icc_max = VR_CFG_AMP(5), |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 82 | .voltage_limit = 1520, |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 83 | .ac_loadline = 1500, |
| 84 | .dc_loadline = 1430, |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 85 | }" |
| 86 | |
| 87 | register "domain_vr_config[VR_IA_CORE]" = "{ |
| 88 | .vr_config_enable = 1, |
| 89 | .psi1threshold = VR_CFG_AMP(20), |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 90 | .psi2threshold = VR_CFG_AMP(2), |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 91 | .psi3threshold = VR_CFG_AMP(1), |
| 92 | .psi3enable = 1, |
| 93 | .psi4enable = 1, |
| 94 | .imon_slope = 0x0, |
| 95 | .imon_offset = 0x0, |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 96 | .icc_max = VR_CFG_AMP(24), |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 97 | .voltage_limit = 1520, |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 98 | .ac_loadline = 570, |
| 99 | .dc_loadline = 483, |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 100 | }" |
| 101 | |
| 102 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| 103 | .vr_config_enable = 1, |
| 104 | .psi1threshold = VR_CFG_AMP(20), |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 105 | .psi2threshold = VR_CFG_AMP(2), |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 106 | .psi3threshold = VR_CFG_AMP(1), |
| 107 | .psi3enable = 1, |
| 108 | .psi4enable = 1, |
| 109 | .imon_slope = 0x0, |
| 110 | .imon_offset = 0x0, |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 111 | .icc_max = VR_CFG_AMP(24), |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 112 | .voltage_limit = 1520, |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 113 | .ac_loadline = 550, |
| 114 | .dc_loadline = 420, |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 115 | }" |
| 116 | |
| 117 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
| 118 | .vr_config_enable = 1, |
| 119 | .psi1threshold = VR_CFG_AMP(20), |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 120 | .psi2threshold = VR_CFG_AMP(2), |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 121 | .psi3threshold = VR_CFG_AMP(1), |
| 122 | .psi3enable = 1, |
| 123 | .psi4enable = 1, |
| 124 | .imon_slope = 0x0, |
| 125 | .imon_offset = 0x0, |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 126 | .icc_max = VR_CFG_AMP(24), |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 127 | .voltage_limit = 1520, |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 128 | .ac_loadline = 550, |
| 129 | .dc_loadline = 420, |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 130 | }" |
| 131 | |
| 132 | # Enable Root port 1. |
| 133 | register "PcieRpEnable[0]" = "1" |
| 134 | # Enable CLKREQ# |
| 135 | register "PcieRpClkReqSupport[0]" = "1" |
| 136 | # RP 1 uses SRCCLKREQ1# |
| 137 | register "PcieRpClkReqNumber[0]" = "1" |
Rizwan Qureshi | 8688536 | 2017-09-05 14:23:27 +0530 | [diff] [blame] | 138 | # RP 1, Enable Advanced Error Reporting |
Rizwan Qureshi | 09703f6 | 2017-09-16 02:01:13 +0530 | [diff] [blame] | 139 | register "PcieRpAdvancedErrorReporting[0]" = "1" |
| 140 | # RP 1, Enable Latency Tolerance Reporting Mechanism |
| 141 | register "PcieRpLtrEnable[0]" = "1" |
Alexander Goncharov | 893c3ae8 | 2023-02-04 15:20:37 +0400 | [diff] [blame] | 142 | # RP 1 uses CLK SRC 1 |
Divya Chellap | e7fb7ce | 2017-12-19 20:16:50 +0530 | [diff] [blame] | 143 | register "PcieRpClkSrcNumber[0]" = "1" |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 144 | |
| 145 | register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 |
| 146 | register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port |
| 147 | register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth |
Wisley Chen | 1fbc192 | 2017-09-05 17:14:06 +0800 | [diff] [blame] | 148 | register "usb2_ports[4]" = "USB2_PORT_MAX(OC1)" # Type-C Port 2 |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 149 | register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port |
| 150 | register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port |
| 151 | |
| 152 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 |
| 153 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 |
| 154 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 155 | |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 156 | # Intel Common SoC Config |
| 157 | #+-------------------+---------------------------+ |
| 158 | #| Field | Value | |
| 159 | #+-------------------+---------------------------+ |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 160 | #| I2C0 | Touchscreen | |
| 161 | #| I2C1 | cr50 TPM. Early init is | |
| 162 | #| | required to set up a BAR | |
| 163 | #| | for TPM communication | |
| 164 | #| | before memory is up | |
| 165 | #| I2C2 | Camera | |
| 166 | #| I2C4 | Camera | |
| 167 | #| I2C5 | Audio | |
Subrata Banik | c077b22 | 2019-08-01 10:50:35 +0530 | [diff] [blame] | 168 | #| pch_thermal_trip | PCH Trip Temperature | |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 169 | #+-------------------+---------------------------+ |
| 170 | register "common_soc_config" = "{ |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 171 | .i2c[0] = { |
Furquan Shaikh | eeab271 | 2017-08-28 14:32:05 -0700 | [diff] [blame] | 172 | .speed = I2C_SPEED_FAST, |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 173 | .speed_config[0] = { |
| 174 | .speed = I2C_SPEED_FAST, |
| 175 | .scl_lcnt = 180, |
| 176 | .scl_hcnt = 85, |
| 177 | .sda_hold = 36, |
| 178 | }, |
| 179 | }, |
| 180 | .i2c[1] = { |
| 181 | .early_init = 1, |
| 182 | .speed = I2C_SPEED_FAST, |
| 183 | .speed_config[0] = { |
| 184 | .speed = I2C_SPEED_FAST, |
| 185 | .scl_lcnt = 190, |
| 186 | .scl_hcnt = 90, |
| 187 | .sda_hold = 36, |
| 188 | }, |
| 189 | }, |
| 190 | .i2c[2] = { |
| 191 | .speed = I2C_SPEED_FAST, |
| 192 | .speed_config[0] = { |
| 193 | .speed = I2C_SPEED_FAST, |
| 194 | .scl_lcnt = 192, |
| 195 | .scl_hcnt = 90, |
| 196 | .sda_hold = 36, |
| 197 | }, |
| 198 | }, |
| 199 | .i2c[4] = { |
| 200 | .speed = I2C_SPEED_FAST, |
| 201 | .speed_config[0] = { |
| 202 | .speed = I2C_SPEED_FAST, |
| 203 | .scl_lcnt = 190, |
| 204 | .scl_hcnt = 90, |
| 205 | .sda_hold = 36, |
| 206 | }, |
| 207 | }, |
| 208 | .i2c[5] = { |
| 209 | .speed = I2C_SPEED_FAST, |
| 210 | .speed_config[0] = { |
| 211 | .speed = I2C_SPEED_FAST, |
| 212 | .scl_lcnt = 190, |
| 213 | .scl_hcnt = 90, |
| 214 | .sda_hold = 36, |
| 215 | }, |
Furquan Shaikh | eeab271 | 2017-08-28 14:32:05 -0700 | [diff] [blame] | 216 | }, |
Subrata Banik | c077b22 | 2019-08-01 10:50:35 +0530 | [diff] [blame] | 217 | .pch_thermal_trip = 75, |
Furquan Shaikh | eeab271 | 2017-08-28 14:32:05 -0700 | [diff] [blame] | 218 | }" |
| 219 | |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 220 | # Touchscreen |
| 221 | register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" |
| 222 | |
Furquan Shaikh | eeab271 | 2017-08-28 14:32:05 -0700 | [diff] [blame] | 223 | # H1 |
Furquan Shaikh | eeab271 | 2017-08-28 14:32:05 -0700 | [diff] [blame] | 224 | # Configure I2C1 for cr50 TPM. Early init is required to set up a BAR |
| 225 | # for TPM communication before memory is up. |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 226 | register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" |
Furquan Shaikh | eeab271 | 2017-08-28 14:32:05 -0700 | [diff] [blame] | 227 | |
| 228 | # Camera |
| 229 | register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" |
Furquan Shaikh | eeab271 | 2017-08-28 14:32:05 -0700 | [diff] [blame] | 230 | |
Furquan Shaikh | eeab271 | 2017-08-28 14:32:05 -0700 | [diff] [blame] | 231 | # Camera |
| 232 | register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" |
Furquan Shaikh | eeab271 | 2017-08-28 14:32:05 -0700 | [diff] [blame] | 233 | |
| 234 | # Audio |
| 235 | register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 236 | |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 237 | # Must leave UART0 enabled or SD/eMMC will not work as PCI |
| 238 | register "SerialIoDevMode" = "{ |
| 239 | [PchSerialIoIndexI2C0] = PchSerialIoPci, |
| 240 | [PchSerialIoIndexI2C1] = PchSerialIoPci, |
| 241 | [PchSerialIoIndexI2C2] = PchSerialIoPci, |
Wisley Chen | d9ccb4e | 2017-09-01 09:21:31 +0800 | [diff] [blame] | 242 | [PchSerialIoIndexI2C3] = PchSerialIoDisabled, |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 243 | [PchSerialIoIndexI2C4] = PchSerialIoPci, |
| 244 | [PchSerialIoIndexI2C5] = PchSerialIoPci, |
Furquan Shaikh | 763b406 | 2017-12-04 12:17:24 -0800 | [diff] [blame] | 245 | [PchSerialIoIndexSpi0] = PchSerialIoDisabled, |
Furquan Shaikh | 296c79c | 2017-06-09 18:41:39 -0700 | [diff] [blame] | 246 | [PchSerialIoIndexSpi1] = PchSerialIoDisabled, |
Angel Pons | 0856494 | 2021-06-04 18:55:03 +0200 | [diff] [blame] | 247 | [PchSerialIoIndexUart0] = PchSerialIoSkipInit, |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 248 | [PchSerialIoIndexUart1] = PchSerialIoDisabled, |
| 249 | [PchSerialIoIndexUart2] = PchSerialIoSkipInit, |
| 250 | }" |
| 251 | |
Sumeet Pawnikar | b4411d3 | 2017-08-10 18:55:12 +0530 | [diff] [blame] | 252 | # PL2 override 15W for KBL-Y |
Sumeet R Pawnikar | 97c5464 | 2020-05-10 01:24:11 +0530 | [diff] [blame] | 253 | register "power_limits_config" = "{ |
| 254 | .tdp_pl2_override = 15, |
| 255 | .psys_pmax = 45, |
| 256 | }" |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 257 | register "tcc_offset" = "10" # TCC of 90C |
| 258 | |
| 259 | # Use default SD card detect GPIO configuration |
Angel Pons | 6bd99f9 | 2021-02-20 00:16:47 +0100 | [diff] [blame] | 260 | register "sdcard_cd_gpio" = "GPP_E15" |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 261 | |
Arthur Heymans | 69cd729 | 2022-11-07 13:52:11 +0100 | [diff] [blame] | 262 | device cpu_cluster 0 on end |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 263 | device domain 0 on |
Marvin Evers | 059476d | 2023-12-04 02:28:25 +0100 | [diff] [blame] | 264 | device ref system_agent on end |
| 265 | device ref igpu on end |
| 266 | device ref sa_thermal on end |
| 267 | device ref imgu on end |
| 268 | device ref south_xhci on end |
| 269 | device ref south_xdci on end |
| 270 | device ref thermal on end |
| 271 | device ref cio on end |
| 272 | device ref i2c0 on |
Wisley Chen | a80a0eb | 2017-07-06 18:02:04 +0800 | [diff] [blame] | 273 | chip drivers/i2c/hid |
| 274 | register "generic.hid" = ""WCOMCOHO"" |
| 275 | register "generic.desc" = ""WCOM Touchscreen"" |
| 276 | register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" |
Matt DeVillier | 86425c8 | 2022-03-28 23:45:14 -0500 | [diff] [blame] | 277 | register "generic.detect" = "1" |
Wisley Chen | a80a0eb | 2017-07-06 18:02:04 +0800 | [diff] [blame] | 278 | register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E3)" |
Furquan Shaikh | ef1a5ed | 2017-10-06 14:06:27 -0700 | [diff] [blame] | 279 | register "generic.reset_delay_ms" = "10" |
Wisley Chen | a80a0eb | 2017-07-06 18:02:04 +0800 | [diff] [blame] | 280 | register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)" |
| 281 | register "generic.enable_delay_ms" = "1" |
Furquan Shaikh | 3ed5969 | 2017-08-28 17:26:28 -0700 | [diff] [blame] | 282 | register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E11)" |
Wisley Chen | a80a0eb | 2017-07-06 18:02:04 +0800 | [diff] [blame] | 283 | register "generic.has_power_resource" = "1" |
Wisley Chen | a80a0eb | 2017-07-06 18:02:04 +0800 | [diff] [blame] | 284 | register "hid_desc_reg_offset" = "0x1" |
| 285 | device i2c 0xA on end |
| 286 | end |
Marvin Evers | 059476d | 2023-12-04 02:28:25 +0100 | [diff] [blame] | 287 | end |
| 288 | device ref i2c1 on |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 289 | chip drivers/i2c/tpm |
| 290 | register "hid" = ""GOOG0005"" |
| 291 | register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)" |
| 292 | device i2c 50 on end |
| 293 | end |
Marvin Evers | 059476d | 2023-12-04 02:28:25 +0100 | [diff] [blame] | 294 | end |
| 295 | device ref i2c2 on end |
| 296 | device ref i2c3 off end |
| 297 | device ref heci1 on end |
| 298 | device ref heci2 off end |
| 299 | device ref csme_ider off end |
| 300 | device ref csme_ktr off end |
| 301 | device ref heci3 off end |
| 302 | device ref sata off end |
| 303 | device ref uart2 on end |
| 304 | device ref i2c5 on |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 305 | chip drivers/i2c/max98927 |
| 306 | register "interleave_mode" = "1" |
Harsha Priya | 130b4a2 | 2017-08-24 14:40:04 -0700 | [diff] [blame] | 307 | register "vmon_slot_no" = "4" |
| 308 | register "imon_slot_no" = "5" |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 309 | register "uid" = "0" |
| 310 | register "desc" = ""SSM4567 Right Speaker Amp"" |
| 311 | register "name" = ""MAXR"" |
| 312 | device i2c 39 on end |
| 313 | end |
| 314 | chip drivers/i2c/max98927 |
| 315 | register "interleave_mode" = "1" |
Harsha Priya | 130b4a2 | 2017-08-24 14:40:04 -0700 | [diff] [blame] | 316 | register "vmon_slot_no" = "6" |
| 317 | register "imon_slot_no" = "7" |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 318 | register "uid" = "1" |
| 319 | register "desc" = ""SSM4567 Left Speaker Amp"" |
| 320 | register "name" = ""MAXL"" |
| 321 | device i2c 3A on end |
| 322 | end |
| 323 | chip drivers/i2c/generic |
| 324 | register "hid" = ""10EC5663"" |
| 325 | register "name" = ""RT53"" |
| 326 | register "desc" = ""Realtek RT5663"" |
| 327 | register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D9)" |
| 328 | register "probed" = "1" |
| 329 | device i2c 13 on end |
| 330 | end |
Marvin Evers | 059476d | 2023-12-04 02:28:25 +0100 | [diff] [blame] | 331 | end |
| 332 | device ref i2c4 on end |
| 333 | device ref pcie_rp1 on |
Furquan Shaikh | a266d1e | 2020-10-04 12:52:54 -0700 | [diff] [blame] | 334 | chip drivers/wifi/generic |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 335 | register "wake" = "GPE0_PCI_EXP" |
| 336 | device pci 00.0 on end |
| 337 | end |
Marvin Evers | 059476d | 2023-12-04 02:28:25 +0100 | [diff] [blame] | 338 | end |
| 339 | device ref pcie_rp2 off end |
| 340 | device ref pcie_rp3 off end |
| 341 | device ref pcie_rp4 off end |
| 342 | device ref pcie_rp5 off end |
| 343 | device ref pcie_rp6 off end |
| 344 | device ref pcie_rp7 off end |
| 345 | device ref pcie_rp8 off end |
| 346 | device ref pcie_rp9 off end |
| 347 | device ref pcie_rp10 off end |
| 348 | device ref pcie_rp11 off end |
| 349 | device ref pcie_rp12 off end |
| 350 | device ref uart0 on end |
| 351 | device ref uart1 off end |
| 352 | device ref gspi0 off end |
| 353 | device ref gspi1 off end |
| 354 | device ref emmc on end |
| 355 | device ref sdio off end |
| 356 | device ref sdxc on end |
| 357 | device ref lpc_espi on |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 358 | chip ec/google/chromeec |
| 359 | device pnp 0c09.0 on end |
| 360 | end |
Marvin Evers | 059476d | 2023-12-04 02:28:25 +0100 | [diff] [blame] | 361 | end |
| 362 | device ref p2sb on end |
| 363 | device ref pmc on end |
| 364 | device ref hda on end |
| 365 | device ref smbus on end |
| 366 | device ref fast_spi on end |
| 367 | device ref gbe off end |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 368 | end |
| 369 | end |