Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
| 3 | # Deep Sx states |
| 4 | register "deep_s3_enable_ac" = "0" |
| 5 | register "deep_s3_enable_dc" = "1" |
| 6 | register "deep_s5_enable_ac" = "1" |
| 7 | register "deep_s5_enable_dc" = "1" |
| 8 | register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN" |
| 9 | |
| 10 | # GPE configuration |
| 11 | # Note that GPE events called out in ASL code rely on this |
| 12 | # route. i.e. If this route changes then the affected GPE |
| 13 | # offset bits also need to be changed. |
| 14 | register "gpe0_dw0" = "GPP_B" |
| 15 | register "gpe0_dw1" = "GPP_D" |
| 16 | register "gpe0_dw2" = "GPP_E" |
| 17 | |
| 18 | # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f |
| 19 | register "gen1_dec" = "0x00fc0801" |
| 20 | register "gen2_dec" = "0x000c0201" |
| 21 | # EC memory map range is 0x900-0x9ff |
| 22 | register "gen3_dec" = "0x00fc0901" |
| 23 | |
| 24 | # Enable DPTF |
| 25 | register "dptf_enable" = "1" |
| 26 | |
Rajat Jain | 2671afc | 2017-07-20 19:31:01 -0700 | [diff] [blame^] | 27 | # Enable S0ix |
| 28 | register "s0ix_enable" = "1" |
| 29 | |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 30 | # FSP Configuration |
| 31 | register "ProbelessTrace" = "0" |
| 32 | register "EnableLan" = "0" |
| 33 | register "EnableSata" = "0" |
| 34 | register "SataSalpSupport" = "0" |
| 35 | register "SataMode" = "0" |
| 36 | register "SataPortsEnable[0]" = "0" |
| 37 | register "EnableAzalia" = "1" |
| 38 | register "DspEnable" = "1" |
| 39 | register "IoBufferOwnership" = "3" |
| 40 | register "EnableTraceHub" = "0" |
| 41 | register "XdciEnable" = "0" |
| 42 | register "SsicPortEnable" = "0" |
| 43 | register "SmbusEnable" = "1" |
| 44 | register "Cio2Enable" = "1" |
| 45 | register "SaImguEnable" = "1" |
| 46 | register "ScsEmmcEnabled" = "1" |
| 47 | register "ScsEmmcHs400Enabled" = "1" |
| 48 | register "ScsSdCardEnabled" = "2" |
| 49 | register "IshEnable" = "0" |
| 50 | register "PttSwitch" = "0" |
| 51 | register "InternalGfx" = "1" |
| 52 | register "SkipExtGfxScan" = "1" |
| 53 | register "Device4Enable" = "1" |
| 54 | register "HeciEnabled" = "0" |
| 55 | register "FspSkipMpInit" = "1" |
| 56 | register "SaGv" = "3" |
| 57 | register "SerialIrqConfigSirqEnable" = "1" |
| 58 | register "PmConfigSlpS3MinAssert" = "2" # 50ms |
| 59 | register "PmConfigSlpS4MinAssert" = "1" # 1s |
| 60 | register "PmConfigSlpSusMinAssert" = "1" # 500ms |
| 61 | register "PmConfigSlpAMinAssert" = "3" # 2s |
| 62 | register "PmTimerDisabled" = "1" |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 63 | |
| 64 | register "pirqa_routing" = "PCH_IRQ11" |
| 65 | register "pirqb_routing" = "PCH_IRQ10" |
| 66 | register "pirqc_routing" = "PCH_IRQ11" |
| 67 | register "pirqd_routing" = "PCH_IRQ11" |
| 68 | register "pirqe_routing" = "PCH_IRQ11" |
| 69 | register "pirqf_routing" = "PCH_IRQ11" |
| 70 | register "pirqg_routing" = "PCH_IRQ11" |
| 71 | register "pirqh_routing" = "PCH_IRQ11" |
| 72 | |
| 73 | # VR Settings Configuration for 4 Domains |
| 74 | #+----------------+-------+-------+-------+-------+ |
| 75 | #| Domain/Setting | SA | IA | GTUS | GTS | |
| 76 | #+----------------+-------+-------+-------+-------+ |
| 77 | #| Psi1Threshold | 20A | 20A | 20A | 20A | |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 78 | #| Psi2Threshold | 2A | 2A | 2A | 2A | |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 79 | #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| 80 | #| Psi3Enable | 1 | 1 | 1 | 1 | |
| 81 | #| Psi4Enable | 1 | 1 | 1 | 1 | |
| 82 | #| ImonSlope | 0 | 0 | 0 | 0 | |
| 83 | #| ImonOffset | 0 | 0 | 0 | 0 | |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 84 | #| IccMax | 5A | 24A | 24A | 24A | |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 85 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 86 | #| AcLoadline | 15 | 5.7 | 5.5 | 5.5 | |
| 87 | #| DcLoadline | 14.3 | 4.83 | 4.2 | 4.2 | |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 88 | #+----------------+-------+-------+-------+-------+ |
| 89 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| 90 | .vr_config_enable = 1, |
| 91 | .psi1threshold = VR_CFG_AMP(20), |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 92 | .psi2threshold = VR_CFG_AMP(2), |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 93 | .psi3threshold = VR_CFG_AMP(1), |
| 94 | .psi3enable = 1, |
| 95 | .psi4enable = 1, |
| 96 | .imon_slope = 0x0, |
| 97 | .imon_offset = 0x0, |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 98 | .icc_max = VR_CFG_AMP(5), |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 99 | .voltage_limit = 1520, |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 100 | .ac_loadline = 1500, |
| 101 | .dc_loadline = 1430, |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 102 | }" |
| 103 | |
| 104 | register "domain_vr_config[VR_IA_CORE]" = "{ |
| 105 | .vr_config_enable = 1, |
| 106 | .psi1threshold = VR_CFG_AMP(20), |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 107 | .psi2threshold = VR_CFG_AMP(2), |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 108 | .psi3threshold = VR_CFG_AMP(1), |
| 109 | .psi3enable = 1, |
| 110 | .psi4enable = 1, |
| 111 | .imon_slope = 0x0, |
| 112 | .imon_offset = 0x0, |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 113 | .icc_max = VR_CFG_AMP(24), |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 114 | .voltage_limit = 1520, |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 115 | .ac_loadline = 570, |
| 116 | .dc_loadline = 483, |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 117 | }" |
| 118 | |
| 119 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| 120 | .vr_config_enable = 1, |
| 121 | .psi1threshold = VR_CFG_AMP(20), |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 122 | .psi2threshold = VR_CFG_AMP(2), |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 123 | .psi3threshold = VR_CFG_AMP(1), |
| 124 | .psi3enable = 1, |
| 125 | .psi4enable = 1, |
| 126 | .imon_slope = 0x0, |
| 127 | .imon_offset = 0x0, |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 128 | .icc_max = VR_CFG_AMP(24), |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 129 | .voltage_limit = 1520, |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 130 | .ac_loadline = 550, |
| 131 | .dc_loadline = 420, |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 132 | }" |
| 133 | |
| 134 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
| 135 | .vr_config_enable = 1, |
| 136 | .psi1threshold = VR_CFG_AMP(20), |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 137 | .psi2threshold = VR_CFG_AMP(2), |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 138 | .psi3threshold = VR_CFG_AMP(1), |
| 139 | .psi3enable = 1, |
| 140 | .psi4enable = 1, |
| 141 | .imon_slope = 0x0, |
| 142 | .imon_offset = 0x0, |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 143 | .icc_max = VR_CFG_AMP(24), |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 144 | .voltage_limit = 1520, |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 145 | .ac_loadline = 550, |
| 146 | .dc_loadline = 420, |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 147 | }" |
| 148 | |
| 149 | # Enable Root port 1. |
| 150 | register "PcieRpEnable[0]" = "1" |
| 151 | # Enable CLKREQ# |
| 152 | register "PcieRpClkReqSupport[0]" = "1" |
| 153 | # RP 1 uses SRCCLKREQ1# |
| 154 | register "PcieRpClkReqNumber[0]" = "1" |
| 155 | |
| 156 | register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 |
| 157 | register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port |
| 158 | register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth |
| 159 | register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2 |
| 160 | register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port |
| 161 | register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port |
| 162 | |
| 163 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 |
| 164 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 |
| 165 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port |
| 166 | register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty |
| 167 | |
| 168 | register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # Touchscreen |
| 169 | register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # H1 |
| 170 | register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" # Camera |
| 171 | register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8" # Pen |
| 172 | register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # Camera |
| 173 | register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" # Audio |
| 174 | |
| 175 | # Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM |
| 176 | # communication before memory is up. |
| 177 | register "gspi[0]" = "{ |
| 178 | .speed_mhz = 1, |
| 179 | .early_init = 1, |
| 180 | }" |
| 181 | |
| 182 | # Configure I2C1 for cr50 TPM. Early init is required to set up a BAR |
| 183 | # for TPM communication before memory is up. |
| 184 | register "i2c[1]" = "{ |
| 185 | .early_init = 1, |
| 186 | }" |
| 187 | |
| 188 | # Must leave UART0 enabled or SD/eMMC will not work as PCI |
| 189 | register "SerialIoDevMode" = "{ |
| 190 | [PchSerialIoIndexI2C0] = PchSerialIoPci, |
| 191 | [PchSerialIoIndexI2C1] = PchSerialIoPci, |
| 192 | [PchSerialIoIndexI2C2] = PchSerialIoPci, |
| 193 | [PchSerialIoIndexI2C3] = PchSerialIoPci, |
| 194 | [PchSerialIoIndexI2C4] = PchSerialIoPci, |
| 195 | [PchSerialIoIndexI2C5] = PchSerialIoPci, |
| 196 | [PchSerialIoIndexSpi0] = PchSerialIoPci, |
Furquan Shaikh | 296c79c | 2017-06-09 18:41:39 -0700 | [diff] [blame] | 197 | [PchSerialIoIndexSpi1] = PchSerialIoDisabled, |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 198 | [PchSerialIoIndexUart0] = PchSerialIoPci, |
| 199 | [PchSerialIoIndexUart1] = PchSerialIoDisabled, |
| 200 | [PchSerialIoIndexUart2] = PchSerialIoSkipInit, |
| 201 | }" |
| 202 | |
| 203 | register "speed_shift_enable" = "1" |
| 204 | register "tdp_pl2_override" = "7" |
| 205 | register "tcc_offset" = "10" # TCC of 90C |
| 206 | |
| 207 | # Use default SD card detect GPIO configuration |
| 208 | register "sdcard_cd_gpio_default" = "GPP_E15" |
| 209 | |
| 210 | device cpu_cluster 0 on |
| 211 | device lapic 0 on end |
| 212 | end |
| 213 | device domain 0 on |
| 214 | device pci 00.0 on end # Host Bridge |
| 215 | device pci 02.0 on end # Integrated Graphics Device |
| 216 | device pci 14.0 on end # USB xHCI |
| 217 | device pci 14.1 off end # USB xDCI (OTG) |
| 218 | device pci 14.2 on end # Thermal Subsystem |
| 219 | device pci 15.0 on |
Wisley Chen | a80a0eb | 2017-07-06 18:02:04 +0800 | [diff] [blame] | 220 | chip drivers/i2c/hid |
| 221 | register "generic.hid" = ""WCOMCOHO"" |
| 222 | register "generic.desc" = ""WCOM Touchscreen"" |
| 223 | register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" |
| 224 | register "generic.probed" = "1" |
| 225 | register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E3)" |
| 226 | register "generic.reset_delay_ms" = "110" |
| 227 | register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)" |
| 228 | register "generic.enable_delay_ms" = "1" |
| 229 | register "generic.has_power_resource" = "1" |
| 230 | register "generic.disable_gpio_export_in_crs" = "1" |
| 231 | register "hid_desc_reg_offset" = "0x1" |
| 232 | device i2c 0xA on end |
| 233 | end |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 234 | chip drivers/i2c/generic |
| 235 | register "hid" = ""ATML0001"" |
| 236 | register "desc" = ""Atmel Touchscreen"" |
| 237 | register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" |
| 238 | register "probed" = "1" |
Furquan Shaikh | 73108de | 2017-05-23 11:56:09 -0700 | [diff] [blame] | 239 | register "has_power_resource" = "1" |
| 240 | register "disable_gpio_export_in_crs" = "1" |
| 241 | register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)" |
| 242 | register "enable_delay_ms" = "250" |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 243 | device i2c 4b on end |
| 244 | end |
| 245 | end # I2C #0 |
| 246 | device pci 15.1 on |
| 247 | chip drivers/i2c/tpm |
| 248 | register "hid" = ""GOOG0005"" |
| 249 | register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)" |
| 250 | device i2c 50 on end |
| 251 | end |
| 252 | end # I2C #1 |
V Sowmya | 5dc1538 | 2017-05-05 14:21:48 +0530 | [diff] [blame] | 253 | device pci 15.2 on end # I2C #2 |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 254 | device pci 15.3 on |
| 255 | chip drivers/i2c/hid |
| 256 | register "generic.hid" = ""WCOM50C1"" |
| 257 | register "generic.desc" = ""WCOM Digitizer"" |
| 258 | register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D1_IRQ)" |
| 259 | register "hid_desc_reg_offset" = "0x1" |
| 260 | device i2c 0x9 on end |
| 261 | end |
| 262 | end # I2C #3 |
| 263 | device pci 16.0 on end # Management Engine Interface 1 |
| 264 | device pci 16.1 off end # Management Engine Interface 2 |
| 265 | device pci 16.2 off end # Management Engine IDE-R |
| 266 | device pci 16.3 off end # Management Engine KT Redirection |
| 267 | device pci 16.4 off end # Management Engine Interface 3 |
| 268 | device pci 17.0 off end # SATA |
| 269 | device pci 19.0 on end # UART #2 |
| 270 | device pci 19.1 on |
| 271 | chip drivers/i2c/max98927 |
| 272 | register "interleave_mode" = "1" |
| 273 | register "uid" = "0" |
| 274 | register "desc" = ""SSM4567 Right Speaker Amp"" |
| 275 | register "name" = ""MAXR"" |
| 276 | device i2c 39 on end |
| 277 | end |
| 278 | chip drivers/i2c/max98927 |
| 279 | register "interleave_mode" = "1" |
| 280 | register "uid" = "1" |
| 281 | register "desc" = ""SSM4567 Left Speaker Amp"" |
| 282 | register "name" = ""MAXL"" |
| 283 | device i2c 3A on end |
| 284 | end |
| 285 | chip drivers/i2c/generic |
| 286 | register "hid" = ""10EC5663"" |
| 287 | register "name" = ""RT53"" |
| 288 | register "desc" = ""Realtek RT5663"" |
| 289 | register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D9)" |
| 290 | register "probed" = "1" |
| 291 | device i2c 13 on end |
| 292 | end |
| 293 | end # I2C #5 |
V Sowmya | 5dc1538 | 2017-05-05 14:21:48 +0530 | [diff] [blame] | 294 | device pci 19.2 on end # I2C #4 |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 295 | device pci 1c.0 on |
| 296 | chip drivers/intel/wifi |
| 297 | register "wake" = "GPE0_PCI_EXP" |
| 298 | device pci 00.0 on end |
| 299 | end |
| 300 | end # PCI Express Port 1 |
| 301 | device pci 1c.1 off end # PCI Express Port 2 |
| 302 | device pci 1c.2 off end # PCI Express Port 3 |
| 303 | device pci 1c.3 off end # PCI Express Port 4 |
| 304 | device pci 1c.4 off end # PCI Express Port 5 |
| 305 | device pci 1c.5 off end # PCI Express Port 6 |
| 306 | device pci 1c.6 off end # PCI Express Port 7 |
| 307 | device pci 1c.7 off end # PCI Express Port 8 |
| 308 | device pci 1d.0 off end # PCI Express Port 9 |
| 309 | device pci 1d.1 off end # PCI Express Port 10 |
| 310 | device pci 1d.2 off end # PCI Express Port 11 |
| 311 | device pci 1d.3 off end # PCI Express Port 12 |
| 312 | device pci 1e.0 on end # UART #0 |
| 313 | device pci 1e.1 off end # UART #1 |
Furquan Shaikh | dec6d4e | 2017-06-09 17:59:07 -0700 | [diff] [blame] | 314 | device pci 1e.2 on |
| 315 | chip drivers/spi/acpi |
| 316 | register "hid" = "ACPI_DT_NAMESPACE_HID" |
| 317 | register "compat_string" = ""google,cr50"" |
| 318 | register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)" |
| 319 | device spi 0 on end |
| 320 | end |
| 321 | end # GSPI #0 |
Furquan Shaikh | 296c79c | 2017-06-09 18:41:39 -0700 | [diff] [blame] | 322 | device pci 1e.3 off end # GSPI #1 |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 323 | device pci 1e.4 on end # eMMC |
| 324 | device pci 1e.5 off end # SDIO |
| 325 | device pci 1e.6 on end # SDCard |
| 326 | device pci 1f.0 on |
| 327 | chip ec/google/chromeec |
| 328 | device pnp 0c09.0 on end |
| 329 | end |
| 330 | end # LPC Interface |
| 331 | device pci 1f.1 on end # P2SB |
| 332 | device pci 1f.2 on end # Power Management Controller |
| 333 | device pci 1f.3 on end # Intel HDA |
| 334 | device pci 1f.4 on end # SMBus |
| 335 | device pci 1f.5 on end # PCH SPI |
| 336 | device pci 1f.6 off end # GbE |
| 337 | end |
| 338 | end |