commit | 085649440bb1604d8492156838813938df10eb83 | [log] [tgz] |
---|---|---|
author | Angel Pons <th3fanbus@gmail.com> | Fri Jun 04 18:55:03 2021 +0200 |
committer | Felix Held <felix-coreboot@felixheld.de> | Tue Aug 31 15:12:45 2021 +0000 |
tree | 4fccb27d683c6372d0b72e1b03e1b966667b4373 | |
parent | 481661e313ddc2efb151cbdb77eeb5237eba5609 [diff] |
mb/google/poppy: Do not let FSP-S init UART 0 FSP-S configures the GPIOs for enabled SerialIO devices. However, Poppy boards only enable UART 0 because it's function 0 of PCI device 30, and the PCI specification requires that function 0 of multifunction devices be implemented if other functions are implemented as well. Nautilus got remedied in commit 8a1f095e50e068e42d378f47c79467e7b6295b7b (mb/google/poppy/variants/nautilus: Update camera power enable GPIOs) by using `PchSerialIoSkipInit` for UART 0, which tells FSP to not touch the SerialIO device. This way, it remains enabled and the GPIO settings will not be overwritten by FSP. However, not all variants do this, but use some UART 0 pads as GPIOs. To prevent any issues, configure UART 0 as `PchSerialIoSkipInit` on all the variants. Change-Id: I7e3a61769ef9e3b348ce84c663f67d3c4c5d9485 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55236 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you're feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.