commit 09703f64940a66345f27d28c0e339c7ac1864b54
author Rizwan Qureshi <rizwan.qureshi@intel.com> Sat Sep 16 02:01:13 2017 +0530
committer Furquan Shaikh <furquan@google.com> Thu Sep 21 03:14:54 2017 +0000
tree a37b6efec21ef2092daecc67199b9e6fcbf58d62
parent 03937391bc80613f4591b5f5c0d00d2607406dc2

mb/google/{poppy,soraka}: Enable LTR for Root port

Enable LTR for Root port 0, where wifi card is connected.

BUG=b:65570878
TEST=After enbaling LTR on port 0 on the MB devicetree, No errors reported
     by AER driver for root port 0.

Change-Id: I222a87fe2094c8424760ccf578e32b9ac042f014
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/21548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajat Jain <rajatja@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/mainboard/google/poppy/variants/soraka/devicetree.cb

diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index ee9c5b7..fa16ae0 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -153,7 +153,9 @@
 	# RP 1 uses SRCCLKREQ1#
 	register "PcieRpClkReqNumber[0]" = "1"
 	# RP 1, Enable Advanced Error Reporting
-	register PcieRpAdvancedErrorReporting[0] = "1"
+	register "PcieRpAdvancedErrorReporting[0]" = "1"
+	# RP 1, Enable Latency Tolerance Reporting Mechanism
+	register "PcieRpLtrEnable[0]" = "1"
 
 	register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)"	# Type-C Port 1
 	register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port