commit 1fbc1927b14f133ef6827f56e4fc31aacc1b8fa9
author Wisley Chen <wisley.chen@quantatw.com> Tue Sep 05 17:14:06 2017 +0800
committer Martin Roth <martinroth@google.com> Wed Sep 13 19:10:10 2017 +0000
tree 3c1678bf74f4cce669b3d532da47a7f46ae79fa6
parent 5613b175de4d692321d21637f99578cd3a8ae4a5

mb/google/soraka: Fine-tune USB 2.0 port4

Fine tune usb 2.0 strength for port 4 to pass eye diagram.

BUG=b:65306272
TEST=build on soraka, measure usb2.0 eye diagram, and result is pass.

Change-Id: I2c79e96e2e3dea1364d7b71af19b57f4c9307fcb
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/21403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/mainboard/google/poppy/variants/soraka/devicetree.cb

diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index de3b231..ee9c5b7 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -158,7 +158,7 @@
 	register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)"	# Type-C Port 1
 	register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port
 	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth
-	register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)"	# Type-C Port 2
+	register "usb2_ports[4]" = "USB2_PORT_MAX(OC1)"		# Type-C Port 2
 	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port
 	register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port