Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
| 3 | # Deep Sx states |
| 4 | register "deep_s3_enable_ac" = "0" |
| 5 | register "deep_s3_enable_dc" = "1" |
| 6 | register "deep_s5_enable_ac" = "1" |
| 7 | register "deep_s5_enable_dc" = "1" |
| 8 | register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN" |
| 9 | |
| 10 | # GPE configuration |
| 11 | # Note that GPE events called out in ASL code rely on this |
| 12 | # route. i.e. If this route changes then the affected GPE |
| 13 | # offset bits also need to be changed. |
| 14 | register "gpe0_dw0" = "GPP_B" |
| 15 | register "gpe0_dw1" = "GPP_D" |
| 16 | register "gpe0_dw2" = "GPP_E" |
| 17 | |
| 18 | # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f |
| 19 | register "gen1_dec" = "0x00fc0801" |
| 20 | register "gen2_dec" = "0x000c0201" |
| 21 | # EC memory map range is 0x900-0x9ff |
| 22 | register "gen3_dec" = "0x00fc0901" |
| 23 | |
| 24 | # Enable DPTF |
| 25 | register "dptf_enable" = "1" |
| 26 | |
Rajat Jain | 2671afc | 2017-07-20 19:31:01 -0700 | [diff] [blame] | 27 | # Enable S0ix |
| 28 | register "s0ix_enable" = "1" |
| 29 | |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 30 | # FSP Configuration |
| 31 | register "ProbelessTrace" = "0" |
| 32 | register "EnableLan" = "0" |
| 33 | register "EnableSata" = "0" |
| 34 | register "SataSalpSupport" = "0" |
| 35 | register "SataMode" = "0" |
| 36 | register "SataPortsEnable[0]" = "0" |
| 37 | register "EnableAzalia" = "1" |
| 38 | register "DspEnable" = "1" |
| 39 | register "IoBufferOwnership" = "3" |
| 40 | register "EnableTraceHub" = "0" |
| 41 | register "XdciEnable" = "0" |
| 42 | register "SsicPortEnable" = "0" |
| 43 | register "SmbusEnable" = "1" |
| 44 | register "Cio2Enable" = "1" |
| 45 | register "SaImguEnable" = "1" |
| 46 | register "ScsEmmcEnabled" = "1" |
| 47 | register "ScsEmmcHs400Enabled" = "1" |
| 48 | register "ScsSdCardEnabled" = "2" |
| 49 | register "IshEnable" = "0" |
| 50 | register "PttSwitch" = "0" |
| 51 | register "InternalGfx" = "1" |
| 52 | register "SkipExtGfxScan" = "1" |
| 53 | register "Device4Enable" = "1" |
| 54 | register "HeciEnabled" = "0" |
| 55 | register "FspSkipMpInit" = "1" |
| 56 | register "SaGv" = "3" |
| 57 | register "SerialIrqConfigSirqEnable" = "1" |
| 58 | register "PmConfigSlpS3MinAssert" = "2" # 50ms |
| 59 | register "PmConfigSlpS4MinAssert" = "1" # 1s |
| 60 | register "PmConfigSlpSusMinAssert" = "1" # 500ms |
| 61 | register "PmConfigSlpAMinAssert" = "3" # 2s |
| 62 | register "PmTimerDisabled" = "1" |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 63 | |
| 64 | register "pirqa_routing" = "PCH_IRQ11" |
| 65 | register "pirqb_routing" = "PCH_IRQ10" |
| 66 | register "pirqc_routing" = "PCH_IRQ11" |
| 67 | register "pirqd_routing" = "PCH_IRQ11" |
| 68 | register "pirqe_routing" = "PCH_IRQ11" |
| 69 | register "pirqf_routing" = "PCH_IRQ11" |
| 70 | register "pirqg_routing" = "PCH_IRQ11" |
| 71 | register "pirqh_routing" = "PCH_IRQ11" |
| 72 | |
| 73 | # VR Settings Configuration for 4 Domains |
| 74 | #+----------------+-------+-------+-------+-------+ |
| 75 | #| Domain/Setting | SA | IA | GTUS | GTS | |
| 76 | #+----------------+-------+-------+-------+-------+ |
| 77 | #| Psi1Threshold | 20A | 20A | 20A | 20A | |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 78 | #| Psi2Threshold | 2A | 2A | 2A | 2A | |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 79 | #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| 80 | #| Psi3Enable | 1 | 1 | 1 | 1 | |
| 81 | #| Psi4Enable | 1 | 1 | 1 | 1 | |
| 82 | #| ImonSlope | 0 | 0 | 0 | 0 | |
| 83 | #| ImonOffset | 0 | 0 | 0 | 0 | |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 84 | #| IccMax | 5A | 24A | 24A | 24A | |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 85 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 86 | #| AcLoadline | 15 | 5.7 | 5.5 | 5.5 | |
| 87 | #| DcLoadline | 14.3 | 4.83 | 4.2 | 4.2 | |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 88 | #+----------------+-------+-------+-------+-------+ |
| 89 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| 90 | .vr_config_enable = 1, |
| 91 | .psi1threshold = VR_CFG_AMP(20), |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 92 | .psi2threshold = VR_CFG_AMP(2), |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 93 | .psi3threshold = VR_CFG_AMP(1), |
| 94 | .psi3enable = 1, |
| 95 | .psi4enable = 1, |
| 96 | .imon_slope = 0x0, |
| 97 | .imon_offset = 0x0, |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 98 | .icc_max = VR_CFG_AMP(5), |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 99 | .voltage_limit = 1520, |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 100 | .ac_loadline = 1500, |
| 101 | .dc_loadline = 1430, |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 102 | }" |
| 103 | |
| 104 | register "domain_vr_config[VR_IA_CORE]" = "{ |
| 105 | .vr_config_enable = 1, |
| 106 | .psi1threshold = VR_CFG_AMP(20), |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 107 | .psi2threshold = VR_CFG_AMP(2), |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 108 | .psi3threshold = VR_CFG_AMP(1), |
| 109 | .psi3enable = 1, |
| 110 | .psi4enable = 1, |
| 111 | .imon_slope = 0x0, |
| 112 | .imon_offset = 0x0, |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 113 | .icc_max = VR_CFG_AMP(24), |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 114 | .voltage_limit = 1520, |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 115 | .ac_loadline = 570, |
| 116 | .dc_loadline = 483, |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 117 | }" |
| 118 | |
| 119 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| 120 | .vr_config_enable = 1, |
| 121 | .psi1threshold = VR_CFG_AMP(20), |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 122 | .psi2threshold = VR_CFG_AMP(2), |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 123 | .psi3threshold = VR_CFG_AMP(1), |
| 124 | .psi3enable = 1, |
| 125 | .psi4enable = 1, |
| 126 | .imon_slope = 0x0, |
| 127 | .imon_offset = 0x0, |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 128 | .icc_max = VR_CFG_AMP(24), |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 129 | .voltage_limit = 1520, |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 130 | .ac_loadline = 550, |
| 131 | .dc_loadline = 420, |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 132 | }" |
| 133 | |
| 134 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
| 135 | .vr_config_enable = 1, |
| 136 | .psi1threshold = VR_CFG_AMP(20), |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 137 | .psi2threshold = VR_CFG_AMP(2), |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 138 | .psi3threshold = VR_CFG_AMP(1), |
| 139 | .psi3enable = 1, |
| 140 | .psi4enable = 1, |
| 141 | .imon_slope = 0x0, |
| 142 | .imon_offset = 0x0, |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 143 | .icc_max = VR_CFG_AMP(24), |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 144 | .voltage_limit = 1520, |
Rajneesh Bhardwaj | 4692e2f | 2017-06-21 16:42:53 +0530 | [diff] [blame] | 145 | .ac_loadline = 550, |
| 146 | .dc_loadline = 420, |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 147 | }" |
| 148 | |
| 149 | # Enable Root port 1. |
| 150 | register "PcieRpEnable[0]" = "1" |
| 151 | # Enable CLKREQ# |
| 152 | register "PcieRpClkReqSupport[0]" = "1" |
| 153 | # RP 1 uses SRCCLKREQ1# |
| 154 | register "PcieRpClkReqNumber[0]" = "1" |
Rizwan Qureshi | 8688536 | 2017-09-05 14:23:27 +0530 | [diff] [blame] | 155 | # RP 1, Enable Advanced Error Reporting |
Rizwan Qureshi | 09703f6 | 2017-09-16 02:01:13 +0530 | [diff] [blame] | 156 | register "PcieRpAdvancedErrorReporting[0]" = "1" |
| 157 | # RP 1, Enable Latency Tolerance Reporting Mechanism |
| 158 | register "PcieRpLtrEnable[0]" = "1" |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 159 | |
| 160 | register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 |
| 161 | register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port |
| 162 | register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth |
Wisley Chen | 1fbc192 | 2017-09-05 17:14:06 +0800 | [diff] [blame] | 163 | register "usb2_ports[4]" = "USB2_PORT_MAX(OC1)" # Type-C Port 2 |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 164 | register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port |
| 165 | register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port |
| 166 | |
| 167 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 |
| 168 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 |
| 169 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port |
| 170 | register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty |
| 171 | |
Furquan Shaikh | eeab271 | 2017-08-28 14:32:05 -0700 | [diff] [blame] | 172 | # Touchscreen |
| 173 | register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" |
| 174 | register "i2c[0]" = "{ |
| 175 | .speed = I2C_SPEED_FAST, |
| 176 | .speed_config[0] = { |
| 177 | .speed = I2C_SPEED_FAST, |
| 178 | .scl_lcnt = 180, |
| 179 | .scl_hcnt = 85, |
| 180 | .sda_hold = 36, |
| 181 | }, |
| 182 | }" |
| 183 | |
| 184 | # H1 |
| 185 | register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" |
| 186 | # Configure I2C1 for cr50 TPM. Early init is required to set up a BAR |
| 187 | # for TPM communication before memory is up. |
| 188 | register "i2c[1]" = "{ |
| 189 | .early_init = 1, |
| 190 | .speed = I2C_SPEED_FAST, |
| 191 | .speed_config[0] = { |
| 192 | .speed = I2C_SPEED_FAST, |
| 193 | .scl_lcnt = 190, |
| 194 | .scl_hcnt = 90, |
| 195 | .sda_hold = 36, |
| 196 | }, |
| 197 | }" |
| 198 | |
| 199 | # Camera |
| 200 | register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" |
| 201 | register "i2c[2]" = "{ |
| 202 | .speed = I2C_SPEED_FAST, |
| 203 | .speed_config[0] = { |
| 204 | .speed = I2C_SPEED_FAST, |
| 205 | .scl_lcnt = 192, |
| 206 | .scl_hcnt = 90, |
| 207 | .sda_hold = 36, |
| 208 | }, |
| 209 | }" |
| 210 | |
Furquan Shaikh | eeab271 | 2017-08-28 14:32:05 -0700 | [diff] [blame] | 211 | # Camera |
| 212 | register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" |
| 213 | register "i2c[4]" = "{ |
| 214 | .speed = I2C_SPEED_FAST, |
| 215 | .speed_config[0] = { |
| 216 | .speed = I2C_SPEED_FAST, |
| 217 | .scl_lcnt = 190, |
| 218 | .scl_hcnt = 90, |
| 219 | .sda_hold = 36, |
| 220 | }, |
| 221 | }" |
| 222 | |
| 223 | # Audio |
| 224 | register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" |
| 225 | register "i2c[5]" = "{ |
| 226 | .speed = I2C_SPEED_FAST, |
| 227 | .speed_config[0] = { |
| 228 | .speed = I2C_SPEED_FAST, |
Furquan Shaikh | 8f08f5f | 2017-09-24 20:50:14 -0700 | [diff] [blame] | 229 | .scl_lcnt = 195, |
| 230 | .scl_hcnt = 90, |
Furquan Shaikh | eeab271 | 2017-08-28 14:32:05 -0700 | [diff] [blame] | 231 | .sda_hold = 36, |
| 232 | }, |
| 233 | }" |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 234 | |
| 235 | # Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM |
| 236 | # communication before memory is up. |
| 237 | register "gspi[0]" = "{ |
| 238 | .speed_mhz = 1, |
| 239 | .early_init = 1, |
| 240 | }" |
| 241 | |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 242 | # Must leave UART0 enabled or SD/eMMC will not work as PCI |
| 243 | register "SerialIoDevMode" = "{ |
| 244 | [PchSerialIoIndexI2C0] = PchSerialIoPci, |
| 245 | [PchSerialIoIndexI2C1] = PchSerialIoPci, |
| 246 | [PchSerialIoIndexI2C2] = PchSerialIoPci, |
Wisley Chen | d9ccb4e | 2017-09-01 09:21:31 +0800 | [diff] [blame] | 247 | [PchSerialIoIndexI2C3] = PchSerialIoDisabled, |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 248 | [PchSerialIoIndexI2C4] = PchSerialIoPci, |
| 249 | [PchSerialIoIndexI2C5] = PchSerialIoPci, |
| 250 | [PchSerialIoIndexSpi0] = PchSerialIoPci, |
Furquan Shaikh | 296c79c | 2017-06-09 18:41:39 -0700 | [diff] [blame] | 251 | [PchSerialIoIndexSpi1] = PchSerialIoDisabled, |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 252 | [PchSerialIoIndexUart0] = PchSerialIoPci, |
| 253 | [PchSerialIoIndexUart1] = PchSerialIoDisabled, |
| 254 | [PchSerialIoIndexUart2] = PchSerialIoSkipInit, |
| 255 | }" |
| 256 | |
| 257 | register "speed_shift_enable" = "1" |
Sumeet Pawnikar | b4411d3 | 2017-08-10 18:55:12 +0530 | [diff] [blame] | 258 | # PL2 override 15W for KBL-Y |
| 259 | register "tdp_pl2_override" = "15" |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 260 | register "tcc_offset" = "10" # TCC of 90C |
| 261 | |
| 262 | # Use default SD card detect GPIO configuration |
| 263 | register "sdcard_cd_gpio_default" = "GPP_E15" |
| 264 | |
Subrata Banik | c204aaa | 2017-08-17 15:49:58 +0530 | [diff] [blame] | 265 | # Lock Down |
| 266 | register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT" |
| 267 | |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 268 | device cpu_cluster 0 on |
| 269 | device lapic 0 on end |
| 270 | end |
| 271 | device domain 0 on |
| 272 | device pci 00.0 on end # Host Bridge |
| 273 | device pci 02.0 on end # Integrated Graphics Device |
| 274 | device pci 14.0 on end # USB xHCI |
| 275 | device pci 14.1 off end # USB xDCI (OTG) |
| 276 | device pci 14.2 on end # Thermal Subsystem |
| 277 | device pci 15.0 on |
Wisley Chen | a80a0eb | 2017-07-06 18:02:04 +0800 | [diff] [blame] | 278 | chip drivers/i2c/hid |
| 279 | register "generic.hid" = ""WCOMCOHO"" |
| 280 | register "generic.desc" = ""WCOM Touchscreen"" |
| 281 | register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" |
| 282 | register "generic.probed" = "1" |
| 283 | register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E3)" |
Furquan Shaikh | ef1a5ed | 2017-10-06 14:06:27 -0700 | [diff] [blame^] | 284 | register "generic.reset_delay_ms" = "10" |
Wisley Chen | a80a0eb | 2017-07-06 18:02:04 +0800 | [diff] [blame] | 285 | register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)" |
| 286 | register "generic.enable_delay_ms" = "1" |
Furquan Shaikh | 3ed5969 | 2017-08-28 17:26:28 -0700 | [diff] [blame] | 287 | register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E11)" |
Wisley Chen | a80a0eb | 2017-07-06 18:02:04 +0800 | [diff] [blame] | 288 | register "generic.has_power_resource" = "1" |
| 289 | register "generic.disable_gpio_export_in_crs" = "1" |
| 290 | register "hid_desc_reg_offset" = "0x1" |
| 291 | device i2c 0xA on end |
| 292 | end |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 293 | end # I2C #0 |
| 294 | device pci 15.1 on |
| 295 | chip drivers/i2c/tpm |
| 296 | register "hid" = ""GOOG0005"" |
| 297 | register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)" |
| 298 | device i2c 50 on end |
| 299 | end |
| 300 | end # I2C #1 |
V Sowmya | 5dc1538 | 2017-05-05 14:21:48 +0530 | [diff] [blame] | 301 | device pci 15.2 on end # I2C #2 |
Wisley Chen | d9ccb4e | 2017-09-01 09:21:31 +0800 | [diff] [blame] | 302 | device pci 15.3 off end # I2C #3 |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 303 | device pci 16.0 on end # Management Engine Interface 1 |
| 304 | device pci 16.1 off end # Management Engine Interface 2 |
| 305 | device pci 16.2 off end # Management Engine IDE-R |
| 306 | device pci 16.3 off end # Management Engine KT Redirection |
| 307 | device pci 16.4 off end # Management Engine Interface 3 |
| 308 | device pci 17.0 off end # SATA |
| 309 | device pci 19.0 on end # UART #2 |
| 310 | device pci 19.1 on |
| 311 | chip drivers/i2c/max98927 |
| 312 | register "interleave_mode" = "1" |
Harsha Priya | 130b4a2 | 2017-08-24 14:40:04 -0700 | [diff] [blame] | 313 | register "vmon_slot_no" = "4" |
| 314 | register "imon_slot_no" = "5" |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 315 | register "uid" = "0" |
| 316 | register "desc" = ""SSM4567 Right Speaker Amp"" |
| 317 | register "name" = ""MAXR"" |
| 318 | device i2c 39 on end |
| 319 | end |
| 320 | chip drivers/i2c/max98927 |
| 321 | register "interleave_mode" = "1" |
Harsha Priya | 130b4a2 | 2017-08-24 14:40:04 -0700 | [diff] [blame] | 322 | register "vmon_slot_no" = "6" |
| 323 | register "imon_slot_no" = "7" |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 324 | register "uid" = "1" |
| 325 | register "desc" = ""SSM4567 Left Speaker Amp"" |
| 326 | register "name" = ""MAXL"" |
| 327 | device i2c 3A on end |
| 328 | end |
| 329 | chip drivers/i2c/generic |
| 330 | register "hid" = ""10EC5663"" |
| 331 | register "name" = ""RT53"" |
| 332 | register "desc" = ""Realtek RT5663"" |
| 333 | register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D9)" |
| 334 | register "probed" = "1" |
| 335 | device i2c 13 on end |
| 336 | end |
| 337 | end # I2C #5 |
V Sowmya | 5dc1538 | 2017-05-05 14:21:48 +0530 | [diff] [blame] | 338 | device pci 19.2 on end # I2C #4 |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 339 | device pci 1c.0 on |
| 340 | chip drivers/intel/wifi |
| 341 | register "wake" = "GPE0_PCI_EXP" |
| 342 | device pci 00.0 on end |
| 343 | end |
| 344 | end # PCI Express Port 1 |
| 345 | device pci 1c.1 off end # PCI Express Port 2 |
| 346 | device pci 1c.2 off end # PCI Express Port 3 |
| 347 | device pci 1c.3 off end # PCI Express Port 4 |
| 348 | device pci 1c.4 off end # PCI Express Port 5 |
| 349 | device pci 1c.5 off end # PCI Express Port 6 |
| 350 | device pci 1c.6 off end # PCI Express Port 7 |
| 351 | device pci 1c.7 off end # PCI Express Port 8 |
| 352 | device pci 1d.0 off end # PCI Express Port 9 |
| 353 | device pci 1d.1 off end # PCI Express Port 10 |
| 354 | device pci 1d.2 off end # PCI Express Port 11 |
| 355 | device pci 1d.3 off end # PCI Express Port 12 |
| 356 | device pci 1e.0 on end # UART #0 |
| 357 | device pci 1e.1 off end # UART #1 |
Furquan Shaikh | dec6d4e | 2017-06-09 17:59:07 -0700 | [diff] [blame] | 358 | device pci 1e.2 on |
| 359 | chip drivers/spi/acpi |
| 360 | register "hid" = "ACPI_DT_NAMESPACE_HID" |
| 361 | register "compat_string" = ""google,cr50"" |
| 362 | register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)" |
| 363 | device spi 0 on end |
| 364 | end |
| 365 | end # GSPI #0 |
Furquan Shaikh | 296c79c | 2017-06-09 18:41:39 -0700 | [diff] [blame] | 366 | device pci 1e.3 off end # GSPI #1 |
Furquan Shaikh | 8888072 | 2017-05-01 14:23:37 -0700 | [diff] [blame] | 367 | device pci 1e.4 on end # eMMC |
| 368 | device pci 1e.5 off end # SDIO |
| 369 | device pci 1e.6 on end # SDCard |
| 370 | device pci 1f.0 on |
| 371 | chip ec/google/chromeec |
| 372 | device pnp 0c09.0 on end |
| 373 | end |
| 374 | end # LPC Interface |
| 375 | device pci 1f.1 on end # P2SB |
| 376 | device pci 1f.2 on end # Power Management Controller |
| 377 | device pci 1f.3 on end # Intel HDA |
| 378 | device pci 1f.4 on end # SMBus |
| 379 | device pci 1f.5 on end # PCH SPI |
| 380 | device pci 1f.6 off end # GbE |
| 381 | end |
| 382 | end |